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Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Battery Management

Texas Instruments TPS650250RHBT

Name: TPS650250RHBT
Brand: Texas Instruments
SKU: TPS650250RHBT
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: TPS650250RHBT

Manufacturer:: Texas Instruments

Category:: Battery Management

Package:: 32-VFQFN Exposed Pad

Datasheet:: TPS650250RHBT.pdf

Description:: IC BAT PWR MGMT LI-ION 1C 32VQFN

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Product details

Overview

TPS650250RHBT from Texas Instruments is a highly integrated power management IC (PMIC) for ARM-based SoCs, featuring three synchronous step-down converters (1.6 A, 0.8 A, 0.8 A), two 200 mA general-purpose LDOs, and one 30 mA always-on Vdd_alive LDO - all in a single 5 mm × 5 mm VQFN-32 package. It supports dynamic voltage scaling for processor core (VDCDC3), operates from 2.5 V to 6 V input, and delivers up to 97% efficiency in DCDC1 for I/O rail generation in mobile applications.

For engineers reviewing the TPS650250RHBT datasheet, TPS650250RHBT pinout, TPS650250RHBT application, or TPS650250RHBT equivalent, key selection criteria include multi-rail sequencing control, MODE-selectable PWM/PFM operation, external resistor-adjustable outputs (VDCDC1–VDCDC3, VLDO1–VLDO2), thermal shutdown (160°C), and 85 μA quiescent current in PFM mode with all regulators enabled.

Technical Context

The TPS650250RHBT integrates three independent buck converters sharing a common 2.25 MHz oscillator but individually enabled via EN_DCDC1/2/3. Each uses synchronous rectification with internal P- and N-channel MOSFETs (R_DS(on) ≤ 698 mΩ), soft-start (750 μs), and feedback via dedicated pins (VDCDC1/VDCDC2/VDCDC3). VDCDC3 supports real-time voltage scaling through dynamic adjustment of its external resistor divider on DEFDCDC3.

All three converters switch between forced PWM (MODE = high) and automatic PFM/PWM hybrid mode (MODE = low) to optimize light-load efficiency. The LDO section includes two externally adjustable 200 mA regulators (VLDO1/VLDO2) with 1.0 V feedback reference and a fixed 1.0 V, 30 mA Vdd_alive LDO with 10 μs load regulation time - designed for always-on system wake-up and RTC functions.

Key Specifications

Parameter	Value and Actual Design Meaning
Input Voltage Range	2.5 V to 6.0 V for all DC-DC inputs (VINDCDC1/2/3) and LDO input (VINLDO) - supports single-cell Li-ion or wide-input industrial rails.
VDCDC1 Output Current	1600 mA max at 3.3 V or 2.8 V - powers system I/O and peripheral rails with 97% peak efficiency.
VDCDC2 & VDCDC3 Current	800 mA each - supplies memory (1.8 V / 2.5 V) and processor core (adjustable 0.6 V to VINDCDC3) with dynamic voltage management.
LDO Output Accuracy	±1% for Vdd_alive; ±2% for VLDO1/VLDO2 - ensures stable voltage for sensitive analog and logic circuitry.
Quiescent Current	85 μA typical in PFM mode with all three DC-DCs and LDOs enabled - extends battery life in standby.
Switching Frequency	2.25 MHz nominal (1.95–2.55 MHz range) - enables use of compact 2.2 μH inductors and 10–22 μF ceramic output capacitors.
Thermal Shutdown	160°C junction temperature with 20°C hysteresis - protects against sustained overload or poor PCB thermal design.

Pinout & Package

TPS650250RHBT is housed in a thermally enhanced 32-pin VQFN package (5.0 mm × 5.0 mm, 0.5 mm pitch) with exposed thermal pad connected internally to AGND. The package supports high-power density layout with separate analog (AGND1/AGND2) and power ground (PGND1/PGND2/PGND3) pins for noise isolation.

Pin/Terminal	Circuit Role	Design Meaning
VINDCDC1, VINDCDC2, VINDCDC3	DC-DC Input Supply	Must be tied together and to VCC; defines input voltage domain for respective converter stages.
L1, L2, L3	Switch Node	Connects to inductor high-side terminal; requires low-inductance routing and local ceramic decoupling.
VDCDC1, VDCDC2, VDCDC3	Feedback Sense	Direct connection to converter output; used with external resistor dividers for adjustable voltage setting.
EN_DCDC1, EN_DCDC2, EN_DCDC3	Enable Control	Active-high logic inputs enabling individual converter startup and sequencing control.
DEFDCDC1, DEFDCDC2	Default Voltage Select	Logic-level inputs selecting fixed 2.8 V / 3.3 V (DCDC1) or 1.8 V / 2.5 V (DCDC2); also accept resistor dividers.
DEFDCDC3	Core Voltage Adjust	Requires external resistor divider only - enables dynamic voltage scaling for ARM processor cores.
VLDO1, VLDO2	LDO Output	200 mA general-purpose outputs; voltage set by FB_LDO1/FB_LDO2 resistive dividers referenced to 1.0 V.
Vdd_alive	Always-On LDO	Fixed 1.0 V, 30 mA output for RTC, wake-up logic, or backup domain - remains active during system sleep.
PWRFAIL / PWRFAIL_SNS	Supply Monitor	Open-drain fault output activated when VBAT falls below 1.0 V threshold (±2%) with 40–60 mV hysteresis.
MODE	Operating Mode Select	High = forced PWM; Low = automatic PFM/PWM transition - balances efficiency vs. output ripple across load range.

Key Features

Feature	Design Value
Three Independent Buck Converters	Enables full power rail separation: VDCDC1 (I/O), VDCDC2 (memory), VDCDC3 (core) - each with dedicated enable, feedback, and inductor interface.
Dynamic Voltage Scaling (DVS)	VDCDC3 output voltage adjusted in real time via DEFDCDC3 resistor divider - supports ARM processor frequency/voltage coordination.
Low Quiescent Current Architecture	85 μA IQ in PFM mode with all rails active - critical for battery-powered devices requiring >1-week standby without recharge.
Dedicated Always-On LDO	Vdd_alive provides regulated 1.0 V at 30 mA with 10 μs load transient response - sustains real-time clock and interrupt wake-up circuitry.
Integrated Power-Fail Detection	PWRFAIL_SNS comparator monitors VBAT and asserts open-drain PWRFAIL signal below 1.0 V - enables graceful system shutdown.
Thermal Protection with Hysteresis	160°C shutdown with 20°C recovery margin prevents thermal runaway during sustained overload or airflow-limited environments.

Applications

Smartphone Power Subsystem	Digital Still Camera (DSC)
Use Scenario: Compact handheld device powered by single Li-ion cell requiring sequenced, low-noise power for application processor, memory, display interface, and camera module. IC Role / Device Role: Central PMIC managing all major voltage domains: VDCDC1 (3.3 V I/O), VDCDC2 (1.8 V DDR), VDCDC3 (1.2 V core), VLDO1 (2.8 V camera sensor), VLDO2 (3.3 V display), Vdd_alive (1.0 V RTC). Use Value: Reduces BOM count by consolidating six discrete regulators into one IC; enables dynamic core voltage scaling to match CPU workload and extend battery runtime.	Use Scenario: Portable imaging device with burst-mode image capture, requiring fast wake-up from deep sleep and stable analog supply for CCD/CMOS sensors. IC Role / Device Role: Primary power controller delivering regulated rails for image processor (VDCDC3), memory buffer (VDCDC2), lens actuator driver (VLDO1), and flash LED bias (VLDO2), while maintaining Vdd_alive for instant-on capability. Use Value: 10 μs Vdd_alive load regulation ensures reliable wake-up timing; PFM mode maintains <100 μA system standby current during idle periods.
Samsung ARM-Based Processor Platform	Split-Supply DSP System
Use Scenario: Reference design for Samsung S5PC110 or similar ARM Cortex-A8/A9 SoC requiring tightly controlled core, memory, and I/O voltages with precise sequencing. IC Role / Device Role: SoC-optimized PMIC providing factory-configurable default voltages (via DEFDCDCx pins) and programmable adjustment for post-silicon tuning of VDCDC3 under varying process corners. Use Value: Eliminates need for external voltage-setting resistors in production; MODE pin allows system firmware to force PWM for deterministic timing or PFM for maximum efficiency.	Use Scenario: Industrial audio or motor control DSP board using dual-voltage logic (1.8 V core, 3.3 V I/O) and isolated analog sections requiring clean, low-noise supplies. IC Role / Device Role: Multi-rail power source generating DSP core (VDCDC3), memory interface (VDCDC2), digital I/O (VDCDC1), and analog bias (VLDO1/VLDO2) with separate AGND/PGND paths to minimize coupling. Use Value: Independent enable pins (EN_DCDCx, EN_LDO) allow flexible power sequencing; 2.25 MHz switching avoids audible noise in sensitive analog signal chains.

Smartphone Power Subsystem

Digital Still Camera (DSC)

Use Scenario: Compact handheld device powered by single Li-ion cell requiring sequenced, low-noise power for application processor, memory, display interface, and camera module.

IC Role / Device Role: Central PMIC managing all major voltage domains: VDCDC1 (3.3 V I/O), VDCDC2 (1.8 V DDR), VDCDC3 (1.2 V core), VLDO1 (2.8 V camera sensor), VLDO2 (3.3 V display), Vdd_alive (1.0 V RTC).

Use Value: Reduces BOM count by consolidating six discrete regulators into one IC; enables dynamic core voltage scaling to match CPU workload and extend battery runtime.

Use Scenario: Portable imaging device with burst-mode image capture, requiring fast wake-up from deep sleep and stable analog supply for CCD/CMOS sensors.

IC Role / Device Role: Primary power controller delivering regulated rails for image processor (VDCDC3), memory buffer (VDCDC2), lens actuator driver (VLDO1), and flash LED bias (VLDO2), while maintaining Vdd_alive for instant-on capability.

Use Value: 10 μs Vdd_alive load regulation ensures reliable wake-up timing; PFM mode maintains <100 μA system standby current during idle periods.

Samsung ARM-Based Processor Platform

Split-Supply DSP System

Use Scenario: Reference design for Samsung S5PC110 or similar ARM Cortex-A8/A9 SoC requiring tightly controlled core, memory, and I/O voltages with precise sequencing.

IC Role / Device Role: SoC-optimized PMIC providing factory-configurable default voltages (via DEFDCDCx pins) and programmable adjustment for post-silicon tuning of VDCDC3 under varying process corners.

Use Value: Eliminates need for external voltage-setting resistors in production; MODE pin allows system firmware to force PWM for deterministic timing or PFM for maximum efficiency.

Use Scenario: Industrial audio or motor control DSP board using dual-voltage logic (1.8 V core, 3.3 V I/O) and isolated analog sections requiring clean, low-noise supplies.

IC Role / Device Role: Multi-rail power source generating DSP core (VDCDC3), memory interface (VDCDC2), digital I/O (VDCDC1), and analog bias (VLDO1/VLDO2) with separate AGND/PGND paths to minimize coupling.

Use Value: Independent enable pins (EN_DCDCx, EN_LDO) allow flexible power sequencing; 2.25 MHz switching avoids audible noise in sensitive analog signal chains.

Equivalent & Alternatives

The following parts are listed as comparable options for similar multi-rail PMIC applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
TPS65910A3RSLR	Higher integration: adds I²C interface, fuel gauge, and real-time clock; 4 buck + 5 LDO channels; 48-pin WQFN.	Targeted at newer OMAP/AM335x platforms requiring host-controlled voltage scaling and battery telemetry.	Choose when I²C programmability, extended LDO count, or integrated fuel gauging are required - not drop-in compatible due to pinout and control architecture differences.
LP87332DRNPT	Lower current: 1.2 A DCDC1, 0.6 A DCDC2/3; no Vdd_alive LDO; 2.5 MHz switching; 28-pin VQFN.	Optimized for cost-sensitive IoT edge nodes with reduced power requirements and simpler sequencing needs.	Choose for space-constrained designs where 800 mA core current suffices and always-on 1.0 V rail is implemented externally.

Compared with TPS650250RHBT, TPS65910A3RSLR offers host-controlled flexibility at higher complexity and cost, while LP87332DRNPT reduces size and cost at the expense of current capability and always-on functionality - making TPS650250RHBT optimal for balanced performance, integration, and legacy ARM platform compatibility.

Availability

TPS650250RHBT is available at Aetrix Electronics and suitable for smartphone power subsystems, digital still cameras, Samsung ARM-based processor platforms, split-supply DSP systems, and GPS navigation modules requiring stable component supply across long-life production cycles.

Supply support for TPS650250RHBT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in high-efficiency DC-DC conversion and battery-powered system solutions.

The TPS650250RHBT belongs to TI's portable power management IC product line, engineered specifically for single-cell Li-ion applications in smartphones, DSCs, and ARM-based computing platforms - emphasizing low IQ, multi-rail integration, and robust thermal management.

FAQ

What input voltage range does the TPS650250RHBT support?

The TPS650250RHBT supports an input voltage range of 2.5 V to 6.0 V across all DC-DC inputs (VINDCDC1/2/3) and the LDO input (VINLDO). This range accommodates single-cell Li-ion (3.0–4.2 V), Li-polymer, or wide-input industrial supplies. All inputs must be tied together and to VCC per the datasheet layout guidelines to ensure proper biasing of internal circuitry.

How is the output voltage of VDCDC3 configured on the TPS650250RHBT?

The TPS650250RHBT requires an external resistor divider connected to the DEFDCDC3 pin to set VDCDC3 output voltage - unlike DEFDCDC1/2, it does not accept logic-level inputs. The output can be adjusted from 0.6 V to VINDCDC3, enabling dynamic voltage scaling for ARM processor cores. The feedback node (VDCDC3) must connect directly to the output rail for accurate regulation.

Does the TPS650250RHBT include built-in power-fail detection?

Yes, the TPS650250RHBT integrates a dedicated power-fail comparator with PWRFAIL_SNS input and open-drain PWRFAIL output. When VBAT drops below 1.0 V (±2%), the comparator triggers PWRFAIL low, allowing the system to initiate controlled shutdown. Hysteresis is 40–60 mV to prevent chatter near the threshold.

What is the quiescent current of the TPS650250RHBT in low-power mode?

The TPS650250RHBT achieves 85 μA typical quiescent current in PFM mode with all three DC-DC converters and all LDOs enabled - measured at VCC = 3.6 V and TA = 25°C. This ultra-low IQ supports extended battery standby in portable devices, and drops further to 16 μA when all regulators are disabled.

Can the TPS650250RHBT generate a fixed 1.0 V always-on supply?

Yes, the TPS650250RHBT includes a dedicated Vdd_alive LDO that delivers a fixed 1.0 V at up to 30 mA. It features 10 μs load regulation time and remains active even when other rails are disabled, making it ideal for powering RTC, wake-up logic, or backup registers in battery-backed systems.

TPS650250RHBT Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: -

Package/Case:: 32-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Function:: Power Management

Battery Chemistry:: Lithium Ion/Polymer

Number of Cells:: 1

Fault Protection:: Over Temperature

Interface:: -

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 32-VQFN (5x5)

TPS650250RHBT FAQ

1.How can I place an order for TPS650250RHBT through Aetrix?

Please submit a Request for Quotation (RFQ) for TPS650250RHBT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for TPS650250RHBT reliable?

The price and inventory of TPS650250RHBT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS650250RHBT is usually 5 days.

3.What payment methods are accepted for TPS650250RHBT?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS650250RHBT transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for TPS650250RHBT?

TPS650250RHBT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your TPS650250RHBT order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for TPS650250RHBT?

For technical support, including TPS650250RHBT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS650250RHBT requirements.

6.How does Aetrix verify that TPS650250RHBT is sourced from the original manufacturer or authorized distributors?

All TPS650250RHBT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS650250RHBT meets industry standards.

7.What is the process for return or replacement of TPS650250RHBT?

All TPS650250RHBT units undergo pre-shipment inspection (PSI). If there is an issue with TPS650250RHBT, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The TPS650250RHBT part is unused and in its original packaging.

Return procedure for TPS650250RHBT:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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