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Texas Instruments TPS65030YZKR
- Part No.:
- TPS65030YZKR
- Manufacturer:
- Texas Instruments
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 25-UFBGA, DSBGA
- Datasheet:
-
TPS65030YZKR.pdf
- Description:
- IC REG QUAD CHRPMP/LNR 25DSBGA
- Quantity:
- Payment:
- Shipping:
Inventory:3,123
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Product details
Overview
TPS65030YZKR from Texas Instruments is a highly integrated power-management IC designed specifically for USB On-The-Go (OTG) systems, featuring three charge pumps and one LDO to generate 5 V/100 mA, 3.3 V/22 mA, 1.5 V/200 mA, and 1.8 V/60 mA outputs from a 3–5 V input. It supports dynamic power-source switchover between Li-ion battery and USB bus voltage, includes sleep mode reducing quiescent current to 8 µA per rail, and integrates Vbus comparator, internal bus switch, and soft-start circuitry. Used in portable OTG host implementations with TUSB6010.
For engineers reviewing the TPS65030YZKR datasheet, TPS65030YZKR pinout, TPS65030YZKR application, or TPS65030YZKR equivalent, key selection considerations include fractional charge pump topology for high efficiency across input range, dual enable-controlled USB-battery switchover (SW_EN1/SW_EN2), sleep-mode LDO fallback for low-power states, and 25-ball DSBGA package constraints for compact handheld PCBs.
Technical Context
The TPS65030YZKR implements three independent regulated output stages: a fractional charge pump for 5 V (Vbus), a dual-mode (x2/LDO) charge pump for 3.3 V (Vout2), a step-down charge pump for 1.5 V (Vout3), and a dedicated LDO for 1.8 V (Vout4). Each output features programmable enable, power-good monitoring, and overcurrent protection.
Its functional modes include LinSkip operation-seamlessly transitioning between constant-frequency PWM and pulse-skipping at light loads-and automatic LDO fallback when input voltage drops below converter threshold (e.g., Vout2 enters LDO mode if VIN < 3.3 V). Sleep mode disables charge pump switching and activates ultra-low-quiescent 100 µA LDOs for Vout2/Vout3/Vout4.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 3 V to 5 V - supports single-cell Li-ion (3–4.2 V) and USB bus (5 V) without external regulation |
| Vbus Output | 5 V ±3% @ 100 mA - fractional charge pump optimized for USB OTG Vbus compliance |
| Vout2 Output | 3.3 V ±3% @ 22 mA - x2 charge pump with LDO fallback in sleep mode |
| Vout3 Output | 1.5 V ±3% @ 200 mA - step-down charge pump with automatic LDO mode below 3.5 V input |
| Vout4 Output | 1.8 V ±3% @ 60 mA - dedicated LDO with independent EN3 control and internal pulldown |
| Switching Frequency | 1 MHz (±17%) - enables use of small ceramic capacitors and minimizes board area |
| Sleep Mode Quiescent Current | 8 µA per enabled rail - reduces system standby power in portable OTG host devices |
Pinout & Package
TPS65030YZKR is housed in a 2.51 mm × 2.70 mm, 25-ball DSBGA (YZK) package with bottom-side I/O terminals. The layout supports high-density portable designs and requires controlled solder reflow due to fine-pitch ball grid.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| EN1 (B3) | Enable for 5-V charge pump | Logic-high enables Vbus; logic-low forces shutdown (<1 µA supply current) |
| EN2 (B4) | Enable for 3.3-V and 1.5-V charge pumps | Single pin controls both Vout2 and Vout3; sequencing ensures Vout2 ramps before Vout3 |
| EN3 (C4) | Enable for 1.8-V LDO | Internal pulldown ensures safe disable if left floating; critical for power sequencing in OTG host boot |
| SLEEP (B2) | Sleep mode control | High = enter sleep mode (LDO-only operation, 8 µA/rail); low = normal charge pump operation |
| SW_EN1 (C3) | Vout3 (1.5 V) source select | Enables internal switch to route Vout3 input from battery to Vbus when Vbus > 4.45 V |
| SW_EN2 (C2) | Vout2 (3.3 V) source select | Enables internal switch to route Vout2 input from battery to Vbus when Vbus > 4.45 V |
| PGood (D3) | Open-drain power-good monitor | Asserts high only when *all enabled* outputs (Vout2/Vout3/Vout4) are within tolerance; 3.1-ms delay after valid rail rise |
| Vbus (E3) | 5-V output / USB bus input | Bi-directional node: output of 5-V charge pump *and* input source for Vout2/Vout3 when SW_ENx asserted |
| CF1A+/CF1A− (C1/E1) | Flying capacitor terminals | Connect 1 µF ceramic capacitor for 5-V fractional charge pump energy transfer |
| CF2+/CF2− (D5/E5) | Flying capacitor terminals | Connect 0.1 µF ceramic capacitor for 3.3-V x2 charge pump |
| CF3+/CF3− (A3/A5) | Flying capacitor terminals | Connect 1 µF ceramic capacitor for 1.5-V step-down charge pump |
| VIN (A1/A2) | Main supply input | Accepts 3–5 V; feeds all regulators; UVLO triggers at 2.91 V rising, 2.79 V falling |
| GND (D4), PGND (E2/B5) | Analog and power ground | Separate AGND (GND) and PGND pins minimize noise coupling into sensitive regulation paths |
Key Features
| Feature | Design Value |
|---|---|
| Integrated USB OTG power architecture | Combines Vbus generation, dual-source switchover (battery/USB), and four regulated rails in one chip-eliminates discrete PMU + switch + LDO solution |
| Dynamic source selection with Vbus comparator | Automatically switches Vout2/Vout3 input between battery and USB bus based on real-time Vbus voltage (>4.45 V threshold with 110 mV hysteresis) |
| LinSkip operating mode | Reduces switching losses at light loads by skipping cycles; maintains 1 MHz frequency under full load for predictable EMI filtering |
| Internal soft-start | Limits inrush current during startup-prevents input voltage sag on high-impedance sources like coin-cell or weak USB ports |
| Overtemperature and overcurrent protection | Thermal shutdown at 155°C with 20°C hysteresis; current limiting per rail prevents damage during short-circuit or overload events |
| Test SRP enable function | Configurable pin supports connectivity test with TUSB6010 (SRP current limit: 1 mA or 100 mA based on SRP logic level) |
Applications
| USB OTG Host in Smartphones | Portable Media Player Power System |
|---|---|
Use Scenario: Smartphone acts as USB host to connect peripherals (keyboard, storage, camera) while operating on battery or USB-powered. IC Role / Device Role / Timing Role: Central PMIC providing all required OTG voltages (Vbus, VDD33, VDD15, VDD18) with seamless battery-to-USB switchover and low-power sleep entry. Use Value: Enables true dual-role OTG operation without external power-path controllers; sleep mode extends standby time by reducing quiescent draw to 24 µA across three rails. |
Use Scenario: Handheld media player powers USB-connected accessories (headset DAC, flash drive) during playback or file transfer. IC Role / Device Role / Timing Role: Regulates and sequences four independent supply rails; manages Vbus ramp-up timing (500 µs) and PGood assertion (3.1 ms delay) to meet USB enumeration timing. Use Value: Eliminates need for discrete charge pumps and LDOs-reduces BOM count by ≥7 components and saves >12 mm² PCB area in 2.5×2.7 mm DSBGA footprint. |
| Digital Camera OTG Functionality | PDA Peripheral Docking Station |
Use Scenario: Digital camera functions as USB host to download images directly to external storage or printer without PC intermediary. IC Role / Device Role / Timing Role: Generates stable 5 V for Vbus and 1.5 V/3.3 V/1.8 V for camera SoC I/O, memory, and sensor interfaces; handles rapid Vbus transitions during plug/unplug. Use Value: Built-in Vbus comparator and fast switchover (<5 µs turn-on/turn-off delay) ensure uninterrupted peripheral operation during USB cable insertion/removal. |
Use Scenario: PDA docks into cradle supplying USB host capability, charging, and display interface-all powered from single Li-ion cell. IC Role / Device Role / Timing Role: Delivers regulated 1.8 V for SDIO interface, 3.3 V for USB transceiver, and 1.5 V for core logic; coordinates enable sequencing via EN2/EN3 to prevent backfeed. Use Value: Internal soft-start and undervoltage lockout (2.91 V) prevent brownout resets during battery discharge-ensures reliable OTG enumeration down to 3.0 V cell voltage. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar USB OTG power management applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65023RSBR | Three buck converters + one LDO; no charge pumps; supports 5-V Vbus via external boost or USB port; higher max output current (up to 1.2 A per buck) | Requires external 5-V generation for Vbus; better suited for systems needing high-current digital rails but not constrained by charge pump efficiency | Select when system uses buck-regulated core supplies and can accommodate external Vbus solution; not drop-in for charge pump–dependent layouts |
| TPS65053RGER | Two buck converters + two LDOs; no Vbus generation; no USB switchover logic; smaller 16-pin QFN package | Lacks integrated Vbus, sleep-mode LDO fallback, and Vbus comparator-requires companion IC for full OTG functionality | Choose for non-OTG applications needing compact dual-buck + dual-LDO; unsuitable as direct replacement where Vbus generation and USB-aware power routing are mandatory |
Compared with TPS65023RSBR and TPS65053RGER, the TPS65030YZKR uniquely integrates fractional charge pumps optimized for USB OTG Vbus and dual-source switchover-enabling complete, self-contained OTG power architecture in minimal area, whereas alternatives require supplemental ICs or compromise on Vbus compliance.
Availability
TPS65030YZKR is available at Aetrix Electronics and suitable for USB OTG host implementations in smartphones, portable media players, and digital cameras requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.
Supply support for TPS65030YZKR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in portable power solutions and USB interface ICs.
The TPS65030YZKR belongs to TI's USB OTG–optimized power management IC product line, engineered to consolidate multiple voltage rails, dynamic source selection, and low-power sleep modes into a single chip for space-constrained mobile host devices.
FAQ
What is the primary application target for the TPS65030YZKR?
The TPS65030YZKR is purpose-built for USB On-The-Go (OTG) host functionality in battery-powered portable devices. It delivers all four required supply rails-5 V for Vbus, 3.3 V and 1.5 V via charge pumps, and 1.8 V via LDO-while enabling automatic switchover between Li-ion battery and USB bus power sources. Its design directly supports integration with TI's TUSB6010 USB OTG transceiver.
How does the TPS65030YZKR handle power-source switchover between battery and USB bus?
The TPS65030YZKR uses dedicated SW_EN1 and SW_EN2 inputs to enable internal analog switches that route Vout3 (1.5 V) and Vout2 (3.3 V) inputs from VIN (battery) to Vbus (USB 5 V) when Vbus exceeds 4.45 V. This switchover is managed autonomously by an integrated Vbus comparator with 110 mV hysteresis, ensuring seamless transition without software intervention or external control logic.
What happens to the TPS65030YZKR outputs during sleep mode?
In sleep mode (SLEEP pin high), the TPS65030YZKR disables all charge pump switching and activates ultra-low-quiescent 100 µA LDOs for Vout2, Vout3, and Vout4-maintaining 3.3 V, 1.5 V, and 1.8 V regulation respectively. Quiescent current drops to 8 µA per enabled rail, and Vout2/Vout3 automatically enter LDO mode regardless of input voltage. Vbus remains disabled unless EN1 is asserted.
Can the TPS65030YZKR generate Vbus from a 3.6-V Li-ion battery?
Yes-the TPS65030YZKR uses a fractional charge pump topology to generate regulated 5 V ±3% at up to 100 mA from a 3–5 V input, including typical 3.6-V nominal Li-ion battery voltage. Efficiency reaches 85% at VIN = 3.6 V and IO = 100 mA, and the device includes soft-start and current limiting to manage inrush and maintain stability during battery-powered Vbus startup.
What are the key thermal characteristics of the TPS65030YZKR in its YZK package?
The TPS65030YZKR in the 25-ball DSBGA (YZK) package has a junction-to-ambient thermal resistance (RθJA) of 87.4°C/W and a junction-to-board resistance (RθJB) of 35°C/W. Its maximum operating junction temperature is 125°C, with thermal shutdown activating at 155°C and hysteresis of 20°C. These values assume standard JEDEC PCB layout with adequate copper pour under the package for heat dissipation.
TPS65030YZKR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 25-UFBGA, DSBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Topology:
- Charge Pump (3), Linear (LDO) (1)
- Number of Outputs:
- 4
- Frequency - Switching:
- 1MHz
- Voltage/Current - Output 1:
- 5V, 100mA
- Voltage/Current - Output 2:
- 1.5V, 200mA
- Voltage/Current - Output 3:
- 3.3V, 22mA
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- No
- Voltage - Supply:
- 3V ~ 5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 25-DSBGA
TPS65030YZKR FAQ
1.How can I place an order for TPS65030YZKR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS65030YZKR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS65030YZKR reliable?
The price and inventory of TPS65030YZKR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS65030YZKR is usually 5 days.
3.What payment methods are accepted for TPS65030YZKR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS65030YZKR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS65030YZKR?
TPS65030YZKR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS65030YZKR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS65030YZKR?
For technical support, including TPS65030YZKR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS65030YZKR requirements.
6.How does Aetrix verify that TPS65030YZKR is sourced from the original manufacturer or authorized distributors?
All TPS65030YZKR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS65030YZKR meets industry standards.
7.What is the process for return or replacement of TPS65030YZKR?
All TPS65030YZKR units undergo pre-shipment inspection (PSI). If there is an issue with TPS65030YZKR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS65030YZKR part is unused and in its original packaging.
Return procedure for TPS65030YZKR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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