Texas Instruments TPS65086401RSKT
- Part No.:
- TPS65086401RSKT
- Manufacturer:
- Texas Instruments
- Category:
- Special Purpose Regulators
- Package:
- 64-VFQFN Exposed Pad
- Datasheet:
-
TPS65086401RSKT.pdf
- Description:
- IC REG CTLR DGTL CAM 9OUT 64VQFN
- Quantity:
- Payment:

- Shipping:

Inventory:1,497
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Product details
Overview
TPS65086401RSKT from Texas Instruments is a configurable multirail power-management IC (PMIC) designed specifically for Xilinx Zynq UltraScale+ MPSoCs (ZU2–ZU5). It integrates three D-CAP2™ step-down controllers (5.6V–21V input), three DCS-Control synchronous buck converters (3V–5.5V input, up to 3A each), three adjustable LDOs, a VTT LDO, and three slew-controlled load switches. It supports I²C DVS control in 10mV/25mV steps and factory OTP configuration for FPGA/MPSoC power sequencing.
For engineers reviewing the TPS65086401RSKT datasheet, TPS65086401RSKT pinout, TPS65086401RSKT application, or TPS65086401RSKT equivalent, this device delivers tightly coordinated rail control for high-density embedded processors-particularly where dynamic voltage scaling, thermal-aware sequencing, and compact 8mm × 8mm VQFN packaging are critical in wall-powered or multi-cell Li-ion systems.
Technical Context
The TPS65086401RSKT implements six independent switching regulators: three high-input-voltage D-CAP2™ controllers (BUCK1/2/6) for core/memory rails and three low-input-voltage DCS-Control converters (BUCK3/4/5) optimized for system I/O and auxiliary supplies. Each regulator supports precise I²C-based DVS with dual-step resolution (10mV for sub-1.67V, 25mV for 1V–3.575V ranges), enabling fine-grained voltage adaptation during processor state transitions.
Its digital architecture includes six configurable GPI pins (CTL1–CTL6) for enable/sleep control, four programmable GPOs for power-good signaling, and an open-drain IRQB interrupt output. Factory-programmed OTP defines default rail voltages-including BUCK1=1.8V, BUCK2=0.85V, BUCK3=0.85V, BUCK4=3.3V, BUCK5=3.3V, BUCK6=1.5V/1.2V/1.1V-and LDOA1=1.8V, LDOA2=1.2V, LDOA3=1.2V-tailored for ZU2–ZU5 SoC power trees.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VIN Range | 5.6V–21V for BUCK1/2/6 controllers; enables direct use with 2S–4S Li-ion or universal AC/DC adapters. |
| Output Current | Up to 3A per DCS-Control buck (BUCK3/4/5); scalable current limit on D-CAP2 controllers via external resistor on ILIM pins. |
| DVS Resolution | 10mV steps (0.41V–1.67V) or 25mV steps (1V–3.575V); supports precise core voltage tuning across P-states. |
| LDO Output Range | LDOA1: 1.35V–3.3V (200mA); LDOA2/A3: 0.7V–1.5V (600mA each); enables flexible I/O and analog supply generation. |
| I²C Speed | Supports standard (100kHz), fast (400kHz), and fast-plus (1MHz) modes; allows real-time rail reconfiguration without bus contention. |
| Package | 64-pin VQFN (RSK), 8.00mm × 8.00mm with exposed thermal pad; achieves RθJB = 4.4°C/W for high-power density layouts. |
| Thermal Shutdown | Programmable critical threshold at 130°C–160°C with 10°C hysteresis; protects against sustained overload in sealed enclosures. |
Pinout & Package
TPS65086401RSKT uses an 8mm × 8mm, 64-pin VQFN package (RSK) with exposed thermal pad requiring connection to PCB ground plane via multiple vias for optimal thermal and electrical performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| FBVOUT1–FBVOUT6 | Remote feedback sense inputs | Enable Kelvin sensing for stable regulation under high-current transients; connect directly to output capacitor terminals. |
| DRVH1–DRVH6 / DRVL1–DRVL6 | High-side and low-side gate drivers | Drive external N-channel MOSFETs; DRVH outputs source/sink ±50mA with <3Ω on-resistance for efficient switching. |
| ILIM1 / ILIM2 / ILIM6 | Current limit set inputs | Accept external resistors to program valley current limit of low-side FETs; reference current = 50µA ±10%. |
| CTL1–CTL6 | Configurable general-purpose inputs | Factory-programmed as enable or sleep-entry signals; support hardware-controlled power-state transitions without I²C overhead. |
| GPO1–GPO4 | Programmable general-purpose outputs | Can mirror power-good status of any rail or be register-controlled; GPO4 is open-drain only; others support push-pull or open-drain. |
| IRQB | Open-drain interrupt output | Asserts on thermal fault, UVLO, overcurrent, or register-access error; requires external pull-up for host CPU notification. |
Key Features
| Feature | Design Value |
|---|---|
| D-CAP2™ topology | Enables fast transient response (<10µs recovery) for processor core rails without external compensation components. |
| DCS-Control™ topology | Delivers high light-load efficiency (>85% at 1mA) and tight DC accuracy (±2%) for memory and I/O supplies. |
| Factory OTP programming | Defines default rail voltages, sequencing order, and CTL/GPO functions-eliminates boot-time I²C initialization for deterministic startup. |
| VTT LDO with VTTFB | Provides DDR termination voltage referenced to BUCK6 output; remote sensing ensures <±1% regulation under load step changes. |
| Slew-controlled load switches | SWA1/SWB1/SWB2 limit inrush current with <96mΩ RDS(ON) at 1.8V input; reduce board-level EMI during power-rail activation. |
Applications
| Programmable Logic Controller | Machine Vision Camera |
|---|---|
Use Scenario: Industrial PLC with Xilinx Zynq UltraScale+ ZU3 executing real-time motion control and fieldbus communication. IC Role / Device Role / Timing Role: Central PMIC managing 12V input conversion to 1.8V core, 3.3V I/O, 1.2V DDR, and 1.5V analog rails with synchronized sequencing. Use Value: Factory-configured OTP eliminates firmware dependency for safe cold-start; D-CAP2™ ensures <50mV droop during 5A core load steps. |
Use Scenario: High-resolution CMOS image sensor interface board using ZU2 SoC with dual MIPI lanes and on-board DDR4 buffer. IC Role / Device Role / Timing Role: Supplies 0.85V core (BUCK2), 0.85V PS PLL (BUCK3), 3.3V I/O (BUCK4), 3.3V sensor bias (BUCK5), and VTT (VTT LDO) with matched timing. Use Value: Dual-step DVS enables dynamic core voltage scaling between idle (0.7V) and capture (0.85V) states; reduces average SoC power by 22%. |
| Video Surveillance System | Embedded PC Platform |
Use Scenario: Multi-channel 4K encoder appliance with ZU5 SoC, H.265 acceleration, and PCIe-connected NVMe storage. IC Role / Device Role / Timing Role: Powers CPU cluster (BUCK1=1.8V), GPU subsystem (BUCK6=1.5V), DDR4 (VTT + BUCK5=3.3V), and PCIe PHY (LDOA1=1.8V). Use Value: Six independent GPOs signal rail readiness to SoC and FPGA logic; enables lockstep boot with <10ms total sequencing time. |
Use Scenario: Fanless embedded PC using ZU4 with dual Gigabit Ethernet, USB 3.0, and eMMC storage. IC Role / Device Role / Timing Role: Generates 1.2V PL logic, 1.8V PS I/O, 3.3V peripherals, 5V USB VBUS, and 1.2V DDR termination-all from single 12V input. Use Value: Integrated 5V LDO (LDO5P0) with automatic switch to external 5V buck improves full-load efficiency by 8% vs. discrete solution. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multirail PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS6508641RSKT | Default BUCK1 = Ext FB (external feedback), BUCK3 = 1.1V/1.2V, BUCK6 = 1.8V; same OTP structure and pinout. | Targeted for ZU2–ZU5 with different core voltage profiles; lacks BUCK1 fixed 1.8V default of TPS65086401RSKT. | Select when SoC requires externally adjustable core voltage or higher BUCK6 output for specific DDR configurations. |
| TPS6508640RSKT | Default BUCK1 = 3.3V, BUCK2 = 0.85V/0.9V, BUCK6 = 1.2V/1.35V; identical topology and package. | Optimized for ZU7–ZU15 devices; higher BUCK1 voltage supports legacy Zynq-7000 compatibility mode. | Choose for migration paths from Zynq-7000 or when 3.3V auxiliary rail is required as primary controller output. |
Compared with TPS65086401RSKT, TPS6508641RSKT offers greater flexibility in core voltage feedback but requires external resistor network for BUCK1, while TPS6508640RSKT provides higher default BUCK1 voltage at the cost of reduced headroom for low-voltage ZU2–ZU5 operation-making TPS65086401RSKT the most balanced choice for new ZU2–ZU5 designs.
Availability
TPS65086401RSKT is available at Aetrix Electronics and suitable for programmable logic controllers, machine vision cameras, video surveillance systems, embedded PCs, and portable ultrasound equipment requiring stable component supply across industrial temperature ranges and long production lifecycles.
Supply support for TPS65086401RSKT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in high-reliability power solutions for FPGA and SoC platforms.
The TPS650864 family was engineered to simplify power delivery for Xilinx Zynq UltraScale+ MPSoCs-integrating controllers, converters, LDOs, and sequencing logic into a single IC to reduce bill-of-materials and layout complexity in space-constrained embedded systems.
FAQ
What is the default output voltage configuration for TPS65086401RSKT?
The TPS65086401RSKT has factory-programmed OTP defaults: BUCK1 = 1.8V, BUCK2 = 0.85V, BUCK3 = 0.85V, BUCK4 = 3.3V, BUCK5 = 3.3V, BUCK6 = 1.5V/1.2V/1.1V (selectable), LDOA1 = 1.8V, LDOA2 = 1.2V, LDOA3 = 1.2V. These values are defined in Section 7.4 of the datasheet and can be modified via I²C after power-up.
Does TPS65086401RSKT support DDR4 VTT termination?
Yes, TPS65086401RSKT includes a dedicated VTT LDO regulated from BUCK6's FBVOUT6 pin, with remote sensing via VTTFB. It delivers precise DDR4 termination voltage (typically 0.6V) with <±1% regulation accuracy and supports dynamic tracking during VDDQ transitions-fully compliant with JEDEC DDR4 specifications.
How does the D-CAP2™ topology in TPS65086401RSKT improve transient response?
The D-CAP2™ topology in TPS65086401RSKT uses internal ripple-based control without external compensation, achieving <10µs load transient recovery time and <50mV droop under 5A step loads. This eliminates phase-margin tuning effort and ensures stable core rail regulation during rapid Zynq UltraScale+ processor state changes.
Can TPS65086401RSKT operate from a 5V input supply?
No-TPS65086401RSKT's D-CAP2™ controllers require minimum 5.6V input (VSYS range: 5.6V–21V). However, its DCS-Control converters (BUCK3/4/5) accept 3V–5.5V inputs, and the integrated LDO5P0 can be powered from an external 5V source via V5ANA, enabling hybrid architectures where 5V feeds auxiliary rails while main input is ≥5.6V.
What thermal management features does TPS65086401RSKT include?
TPS65086401RSKT integrates die temperature monitoring with two thresholds: THOT (110°C–120°C) for warning alerts and TCRIT (130°C–160°C) for automatic shutdown. It reports status via IRQB and registers, and its 8mm × 8mm VQFN package achieves RθJB = 4.4°C/W-enabling >3W dissipation with standard 2-layer PCB copper pours.
TPS65086401RSKT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- D-CAP2™
- Package/Case:
- 64-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- Controller/Converter, Digital Cameras
- Voltage - Input:
- 5.6V ~ 21V
- Number of Outputs:
- 9
- Voltage - Output:
- Multiple
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 64-VQFN (8x8)
TPS65086401RSKT FAQ
1.How can I place an order for TPS65086401RSKT through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS65086401RSKT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS65086401RSKT reliable?
The price and inventory of TPS65086401RSKT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS65086401RSKT is usually 5 days.
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Once your TPS65086401RSKT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS65086401RSKT?
For technical support, including TPS65086401RSKT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS65086401RSKT requirements.
6.How does Aetrix verify that TPS65086401RSKT is sourced from the original manufacturer or authorized distributors?
All TPS65086401RSKT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS65086401RSKT meets industry standards.
7.What is the process for return or replacement of TPS65086401RSKT?
All TPS65086401RSKT units undergo pre-shipment inspection (PSI). If there is an issue with TPS65086401RSKT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS65086401RSKT part is unused and in its original packaging.
Return procedure for TPS65086401RSKT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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