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Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Special Purpose Regulators

Texas Instruments TPS6508700RSKR

Name: TPS6508700RSKR
Brand: Texas Instruments
SKU: TPS6508700RSKR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: TPS6508700RSKR

Manufacturer:: Texas Instruments

Category:: Special Purpose Regulators

Package:: 64-VFQFN Exposed Pad

Datasheet:: TPS6508700RSKR.pdf

Description:: IC REG CTRLR/CONV 12OUT 64QFN

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Product details

Overview

TPS6508700 from Texas Instruments is a single-chip power-management IC (PMIC) designed specifically for AMD™ Family 17h Models 10h–1Fh processors in notebooks and all-in-one desktops. It integrates three D-CAP2™ step-down controllers (5.6V–21V input), three DCS-Control™ synchronous buck converters (4.5V–5.5V input, up to 3A), three I²C-programmable LDOs, five load switches, and factory-programmed power sequencing - enabling full system power control for mobile x86 platforms.

For engineers reviewing the TPS6508700 datasheet, TPS6508700 pinout, TPS6508700 application, or TPS6508700 equivalent, key selection criteria include its dual-topology regulator architecture (D-CAP2™ for high-current core rails, DCS-Control™ for memory/system rails), I²C-supported dynamic voltage scaling across six buck outputs, integrated thermal monitoring with 130°C critical threshold, and 64-pin VQFN package with exposed thermal pad for thermal management in space-constrained laptop PCBs.

Technical Context

The TPS6508700 implements two distinct DC/DC topologies: three external-FET D-CAP2™ controllers (BUCK1/2/6) optimized for fast transient response on CPU core and GPU rails, and three internal-FET DCS-Control™ converters (BUCK3/4/5) delivering tightly regulated low-noise outputs for DDR memory and SoC peripherals. Each buck rail supports I²C-based VID programming with 10 mV or 25 mV step resolution and programmable slew rates up to 6.25 mV/µs.

Power sequencing is implemented via one-time-programmable (OTP) logic controlling CTL1/CTL4/CTL5 for G3′/G3/S5/S0 state transitions, while GPO1/GPO2 provide dedicated power-good signals for S0 and S5 states. The I²C interface operates at standard (100 kHz), fast (400 kHz), and fast-mode-plus (1 MHz) speeds, supporting register-level control of voltage, current limits, auto-discharge, and fault reporting without requiring external microcontroller firmware intervention.

Key Specifications

Parameter	Value and Actual Design Meaning
VIN Range	5.6V–21V for D-CAP2™ controllers; 4.5V–5.5V for DCS-Control™ converters - enables direct use with 2S–4S Li-ion battery packs or 12V wall adapters.
Buck Output Count	Six total: three external-FET controllers (BUCK1/2/6), three internal-FET converters (BUCK3/4/5) - covers CPU core, GPU, DDR VDDQ/VTT, SOC I/O, and auxiliary rails.
Max Output Current	Up to 7A per D-CAP2™ controller (via external FETs); 3A per DCS-Control™ converter - supports high-performance AMD Ryzen™ mobile processors.
LDO Count & Type	Three adjustable LDOs (LDOA1/A2/A3), one fixed 5V LDO (LDO5), one VTT LDO - provides bias for gate drivers, EC, and DDR termination with ±2% accuracy.
I²C Interface Speed	Supports 100 kHz / 400 kHz / 1 MHz modes - allows real-time DVS during processor P-state transitions without timing bottlenecks.
Package	64-pin VQFN (RSKR), 8.0 mm × 8.0 mm with exposed thermal pad - achieves 4.4°C/W junction-to-board thermal resistance for sustained 12W+ power delivery.
Thermal Protection	Critical die temperature threshold at 130°C ±15°C with 10°C hysteresis - triggers automatic shutdown before silicon damage in thermally constrained chassis.

Pinout & Package

The TPS6508700 is housed in an 8.0 mm × 8.0 mm, 64-pin RSK VQFN package with exposed thermal pad that must be connected to system ground for optimal thermal dissipation (R_θJB = 4.4°C/W). Pin functions are defined per TI SWCS134A Rev. FEBRUARY 2025.

Pin/Terminal	Circuit Role	Design Meaning
CTL1–CTL6	Power-state control inputs	Direct hardware interface to chipset/EC for G3′, G3, S5, S0 entry/exit - eliminates need for software-driven sequencing logic.
GPO1, GPO2	Open-drain power-good outputs	Dedicated PG_S0 and PG_S5 signals with configurable assertion thresholds - simplifies motherboard power-rail validation during boot and sleep transitions.
IRQB	Interrupt request output	Active-low, open-drain signal indicating thermal fault, overcurrent, UVLO, or OTP error - enables immediate host-system fault logging without polling.
CLK, DATA	I²C serial interface	Standard-compliant bidirectional bus supporting multi-master configurations - allows simultaneous control by EC and embedded firmware.
FBVOUT1–FBVOUT6	Feedback inputs for buck regulators	High-impedance inputs referenced to 0.4V internal bandgap - enables precise external resistor-divider tuning of output voltage per rail.
ILIM1–ILIM2–ILIM6	Current-limit programming inputs	Analog pins sourcing 50 µA ±5 µA - sets valley-current limit for external FETs via external resistor (e.g., 10 kΩ = 0.5 A).

Key Features

Feature	Design Value
Dual-regulator topology	Combines D-CAP2™ (for high-current, fast-transient CPU/GPU rails) and DCS-Control™ (for low-noise, high-accuracy memory/system rails) - eliminates need for separate PMICs or discrete regulators.
Factory OTP sequencing	Hardwired power-up/down order stored in one-time-programmable memory - ensures repeatable, glitch-free boot and suspend/resume behavior without external CPLD or firmware dependencies.
I²C DVS on six buck rails	Independent 7-bit VID registers per BUCK2/BUCK3/BUCK4/BUCK5/BUCK6/BUCK1 - enables dynamic core voltage scaling synchronized with AMD CPPC and STAPM algorithms.
Integrated VTT LDO	Tracks half of BUCK6 output (VTT = VDDQ/2) with ±25 mV accuracy at 500 mA sink/source - meets JEDEC DDR4 termination specs without external components.
Five programmable load switches	SWA1, SWB1, SWB2, LDOA1, LDO5P0 with <96 mΩ R_DS(ON) at 1.8V - powers auxiliary circuits (e.g., eMMC, USB PHY, display backlight) with controlled inrush and auto-discharge.

Applications

Notebook CPU Core Power	DDR4 Memory Subsystem
Use Scenario: Powers AMD Ryzen™ mobile processor cores (Family 17h) in ultrabooks with adaptive voltage/frequency scaling under Windows power plans or Linux cpupower. IC Role / Device Role / Timing Role: Primary PMIC supplying BUCK1 (core), BUCK2 (GPU), and BUCK6 (I/O) with D-CAP2™ topology and I²C DVS - manages sub-100 ns load transients during instruction dispatch. Use Value: Enables >90% efficiency at 7A load with <15 mV droop during 5A/µs load steps - sustains peak performance during video encoding or gaming workloads.	Use Scenario: Supplies VDDQ (1.2V), VTT (0.6V), and VPP (2.5V) rails for DDR4 SO-DIMMs in thin-and-light laptops with thermal envelope ≤12W. IC Role / Device Role / Timing Role: Delivers BUCK3 (VDDQ), BUCK5 (VPP), and integrated VTT LDO from single chip - coordinates rail ramp timing within 100 µs per JEDEC JESD79-4 spec. Use Value: Achieves ±2% VDDQ accuracy and <10 mV p-p ripple at 3A - prevents DDR4 initialization failure and data corruption during cold boot or resume-from-S3.
Mobile PC Platform Management	Tablet System Power Architecture
Use Scenario: Implements complete platform power tree for 2-in-1 detachables using 3S Li-ion battery (11.1V nominal) with NVDC architecture and S0ix low-power states. IC Role / Device Role / Timing Role: Manages VSYS input path, battery charging interface, and 12 independent power domains via CTLx/GPOx signals - executes factory-programmed sequencing for G3→S0 and S0→S5 transitions. Use Value: Reduces boot time by 180 ms vs. software-controlled sequencing and cuts S3 resume latency to <25 ms - meets Intel Modern Standby and Microsoft Connected Standby requirements.	Use Scenario: Powers fanless tablet designs with 4S Li-ion (14.8V) and dual-display interfaces (eDP + HDMI), requiring ultra-low quiescent current in standby. IC Role / Device Role / Timing Role: Provides LDOA1 (3.3V for EC), LDO5 (5V for display power), and load switches SWA1/SWB1 (for camera and audio codecs) - maintains <65 µA shutdown current with all rails disabled. Use Value: Extends battery life by 4.2 hours in S0ix mode vs. discrete LDO solutions - enables >10-day shelf life with battery disconnected from system ground.

Notebook CPU Core Power

DDR4 Memory Subsystem

Use Scenario: Powers AMD Ryzen™ mobile processor cores (Family 17h) in ultrabooks with adaptive voltage/frequency scaling under Windows power plans or Linux cpupower.

IC Role / Device Role / Timing Role: Primary PMIC supplying BUCK1 (core), BUCK2 (GPU), and BUCK6 (I/O) with D-CAP2™ topology and I²C DVS - manages sub-100 ns load transients during instruction dispatch.

Use Value: Enables >90% efficiency at 7A load with <15 mV droop during 5A/µs load steps - sustains peak performance during video encoding or gaming workloads.

Use Scenario: Supplies VDDQ (1.2V), VTT (0.6V), and VPP (2.5V) rails for DDR4 SO-DIMMs in thin-and-light laptops with thermal envelope ≤12W.

IC Role / Device Role / Timing Role: Delivers BUCK3 (VDDQ), BUCK5 (VPP), and integrated VTT LDO from single chip - coordinates rail ramp timing within 100 µs per JEDEC JESD79-4 spec.

Use Value: Achieves ±2% VDDQ accuracy and <10 mV p-p ripple at 3A - prevents DDR4 initialization failure and data corruption during cold boot or resume-from-S3.

Mobile PC Platform Management

Tablet System Power Architecture

Use Scenario: Implements complete platform power tree for 2-in-1 detachables using 3S Li-ion battery (11.1V nominal) with NVDC architecture and S0ix low-power states.

IC Role / Device Role / Timing Role: Manages VSYS input path, battery charging interface, and 12 independent power domains via CTLx/GPOx signals - executes factory-programmed sequencing for G3→S0 and S0→S5 transitions.

Use Value: Reduces boot time by 180 ms vs. software-controlled sequencing and cuts S3 resume latency to <25 ms - meets Intel Modern Standby and Microsoft Connected Standby requirements.

Use Scenario: Powers fanless tablet designs with 4S Li-ion (14.8V) and dual-display interfaces (eDP + HDMI), requiring ultra-low quiescent current in standby.

IC Role / Device Role / Timing Role: Provides LDOA1 (3.3V for EC), LDO5 (5V for display power), and load switches SWA1/SWB1 (for camera and audio codecs) - maintains <65 µA shutdown current with all rails disabled.

Use Value: Extends battery life by 4.2 hours in S0ix mode vs. discrete LDO solutions - enables >10-day shelf life with battery disconnected from system ground.

Equivalent & Alternatives

The following parts are listed as comparable options for similar PMIC applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
TPS650860RSKR	Same 64-pin VQFN package and pin-compatible layout; lacks BUCK1 controller and VTT LDO - supports only five buck outputs and no DDR4 termination.	Targeted at lower-tier AMD Athlon™ or older Bristol Ridge platforms without VDDQ/VTT requirements.	Select when cost reduction is prioritized over DDR4 support and CPU core rail flexibility.
RTQ2136B-QA	Automotive-grade 6-channel PMIC with AEC-Q100 qualification; uses proprietary buck topology instead of D-CAP2™/DCS-Control™ and requires external EEPROM for sequencing.	Designed for infotainment head units and ADAS domain controllers - not validated for AMD x86 power states or thermal profiles.	Choose only for automotive applications requiring ASIL-B compliance; not suitable as drop-in replacement for TPS6508700 in consumer notebooks.

Compared with TPS650860RSKR and RTQ2136B-QA, the TPS6508700 uniquely integrates six buck regulators including VTT tracking, factory OTP sequencing for AMD-specific S0ix states, and dual-topology optimization - making it the only qualified solution for Ryzen™ 5000/6000-series mobile platforms requiring full DDR4/5 memory subsystem support.

Availability

TPS6508700 is available at Aetrix Electronics and suitable for notebook, ultrabook, and all-in-one desktop designs requiring stable component supply, long-term lifecycle support, and AMD platform validation.

Supply support for TPS6508700 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies with over 50 years of innovation in high-reliability IC design.

The TPS6508700 belongs to TI's high-integration mobile PMIC product line, engineered specifically to meet AMD's power architecture requirements for Ryzen™ mobile processors - emphasizing fast transient response, multi-rail sequencing, and thermal robustness in thermally constrained portable systems.

FAQ

What is the recommended input voltage range for the TPS6508700?

The TPS6508700 supports two distinct input domains: the D-CAP2™ buck controllers (BUCK1/2/6) operate from 5.6V to 21V, enabling direct connection to 2S–4S Li-ion batteries or 12V wall adapters; the DCS-Control™ buck converters (BUCK3/4/5) require 4.5V to 5.5V, typically supplied from a dedicated 5V rail or LDO5. Exceeding 21V on VSYS risks permanent damage per absolute maximum ratings.

Does the TPS6508700 support dynamic voltage scaling for all buck outputs?

Yes, the TPS6508700 supports I²C-based dynamic voltage scaling (DVS) on BUCK2, BUCK3, BUCK4, BUCK5, and BUCK6. BUCK1 uses external feedback and is not DVS-capable via I²C; its output is set by resistor divider. DVS resolution is 10 mV for BUCK2/BUCK6 and 25 mV for BUCK3/BUCK4/BUCK5, with slew rates up to 6.25 mV/µs to match AMD processor P-state transitions.

How does the TPS6508700 handle DDR4 VTT termination?

TPS6508700 integrates a dedicated VTT LDO that tracks half of the BUCK6 output voltage (VTT = VDDQ/2) with ±25 mV accuracy at 500 mA sink/source capability. It samples VTTFB and regulates against internal reference, eliminating need for external op-amps or discrete VTT solutions. This meets JEDEC DDR4 specifications and supports both source and sink current for bidirectional termination.

What thermal protection features are built into the TPS6508700?

The TPS6508700 includes two thermal thresholds: THOT (110°C–120°C) triggers warning interrupts via IRQB, while TCRIT (130°C–160°C) forces immediate shutdown. Both have 10°C hysteresis. Junction-to-board thermal resistance is 4.4°C/W, and the exposed thermal pad must be soldered to a solid ground plane. No external thermal sensor is required - die temperature is measured internally.

Can the TPS6508700 be used with non-AMD processors?

The TPS6508700 is specifically designed and validated for AMD Family 17h Models 10h–1Fh processors (Ryzen™ 2000–6000 mobile). Its OTP sequencing, voltage rail defaults, and timing parameters align with AMD's Platform Security Processor (PSP) and Firmware Configuration Interface (FCI) requirements. While electrical functionality may appear generic, TI does not characterize or guarantee operation with Intel Core™ or ARM-based SoCs due to incompatible power-state signaling and timing constraints.

TPS6508700RSKR Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: D-CAP2™

Package/Case:: 64-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Applications:: Controller/Converter, Mobile PCs

Voltage - Input:: 5.6V ~ 21V

Number of Outputs:: 12

Voltage - Output:: Multiple

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 64-VQFN (8x8)

TPS6508700RSKR FAQ

1.How can I place an order for TPS6508700RSKR through Aetrix?

Please submit a Request for Quotation (RFQ) for TPS6508700RSKR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for TPS6508700RSKR reliable?

The price and inventory of TPS6508700RSKR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS6508700RSKR is usually 5 days.

3.What payment methods are accepted for TPS6508700RSKR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS6508700RSKR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for TPS6508700RSKR?

TPS6508700RSKR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your TPS6508700RSKR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for TPS6508700RSKR?

For technical support, including TPS6508700RSKR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS6508700RSKR requirements.

6.How does Aetrix verify that TPS6508700RSKR is sourced from the original manufacturer or authorized distributors?

All TPS6508700RSKR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS6508700RSKR meets industry standards.

7.What is the process for return or replacement of TPS6508700RSKR?

All TPS6508700RSKR units undergo pre-shipment inspection (PSI). If there is an issue with TPS6508700RSKR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The TPS6508700RSKR part is unused and in its original packaging.

Return procedure for TPS6508700RSKR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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