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Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Special Purpose Regulators

Texas Instruments TPS650940A0RSKR

Name: TPS650940A0RSKR
Brand: Texas Instruments
SKU: TPS650940A0RSKR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: TPS650940A0RSKR

Manufacturer:: Texas Instruments

Category:: Special Purpose Regulators

Package:: 64-VFQFN Exposed Pad

Datasheet:: TPS650940A0RSKR.pdf

Description:: IC REG CTRLR/CONV 12OUT 64QFN

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Product details

Overview

TPS650940A0RSKR from Texas Instruments is a power-management IC (PMIC) designed for Intel™ Apollo Lake platforms, integrating six synchronous buck regulators (three controllers + three converters), three adjustable LDOs, VTT termination, and three load switches. It delivers 5A/7A/21A output capability across BUCK1/BUCK6/BUCK2, supports I²C dynamic voltage scaling (0.5V–1.45V in 10mV steps), and operates from 5.6V–21V input for battery- or wall-powered mobile computing systems.

For engineers reviewing the TPS650940A0RSKR datasheet, TPS650940A0RSKR pinout, TPS650940A0RSKR application, or TPS650940A0RSKR equivalent, key selection considerations include OTP-configured DDR interface support (LPDDR4), VTT enablement status, BUCK3–BUCK5 forced-PWM mode requirement, and thermal pad routing for 8mm × 8mm VQFN-64 package integration in space-constrained ultrabook and tablet designs.

Technical Context

The TPS650940A0RSKR implements D-CAP2™ topology for BUCK1/BUCK2/BUCK6 controllers-enabling fast transient response without external compensation-and dcs-control for BUCK3/BUCK4/BUCK5 converters to maintain stability under light-load conditions. Its OTP configuration (DEVICEID = 0x08) fixes LPDDR4 support, 1.1V BUCK6 default output, VTT enabled, and SLP_S4B-controlled SWB1_2, distinguishing it from other TPS65094x variants.

I²C interface (address 0x5E) enables full rail control-including DVS, sequencing, fault reporting via IRQB, and thermal monitoring (THOT = 115°C)-while dedicated power-state pins (SLP_S0B/SLP_S3B/SLP_S4B) coordinate with Intel PCH for connected standby, S3, and S4 entry/exit. The PMIC integrates internal 3.3V/5V LDOs and references (VREF = 1.25V ±0.5%) for system biasing.

Key Specifications

Parameter	Value and Actual Design Meaning
Input Voltage Range	5.6V–21V for main rails; 4.5V–5.5V for BUCK3–BUCK5 - supports dual-input architectures (battery + adapter)
BUCK2 Output Current	21A (with external FETs) - powers Intel VCCGI rail requiring high-current, low-voltage delivery
DVS Resolution	10mV steps from 0.5V–1.45V on BUCK1/BUCK2 - enables fine-grained CPU core voltage optimization during active/idle states
I²C Speed Support	Standard (100kHz), Fast (400kHz), Fast Plus (1MHz) - allows rapid register updates for dynamic power management
Thermal Resistance	R_θJA = 25.8°C/W (VQFN-64) - requires thermal pad connection to PCB ground plane for reliable 125°C junction operation
OTP Configuration	TPS650940 variant: LPDDR4, VTT enabled, BUCK6 = 1.1V, SWB1_2 controlled by SLP_S4B - defines memory interface compatibility and power-state behavior
Shutdown Current	65µA - ensures minimal battery drain in G3 state for long-term storage of portable devices

Pinout & Package

TPS650940A0RSKR is housed in an 8mm × 8mm single-row VQFN-64 package (RSK) with exposed thermal pad requiring direct connection to PCB ground plane for thermal and electrical integrity.

Pin/Terminal	Circuit Role	Design Meaning
FBGND2 / FBVOUT2	Remote feedback sense pair for BUCK2	Enables accurate VCCGI regulation by sensing at SoC VSS/VCC points - critical for Intel VR compliance
DRVH2 / DRVL2 / BOOT2	High-side/low-side gate drivers + bootstrap for BUCK2	Drives external FETs; BOOT2 requires 100nF ceramic cap to SW2 - defines switching efficiency and layout constraints
ILIM2	Current limit set pin for BUCK2	Resistor-to-ground sets valley current limit (ILIMREF = 50µA ±10%) - calibrates overcurrent protection for 21A rail
SLP_S4B	Power-state input	Controls SWB1/SWB2 load switches and transitions into S4 - ties directly to Intel PCH sleep signaling protocol
VTT / VTTFB / PVINVTT	VTT LDO inputs and outputs	VTT = VDDQ/2; VTTFB provides remote sensing - meets DDR3/DDR4 termination accuracy requirements (±1% typical)
DATA / CLK	I²C bidirectional data/clock	Address 0x5E; supports Fast Plus mode - enables real-time rail reconfiguration without host processor intervention

Key Features

Feature	Design Value
D-CAP2™ Buck Controllers	Eliminates need for external compensation components on BUCK1/BUCK2/BUCK6 - reduces BOM count and layout area for high-current rails
dcs-Control Buck Converters	Maintains fixed-frequency PWM operation in BUCK3/BUCK4/BUCK5 even at light loads - prevents audible noise and improves EMI predictability
OTP-Programmed LPDDR4 Support	Fixed 1.1V BUCK6 output and enabled VTT - ensures out-of-box compatibility with Intel Apollo Lake LPDDR4 memory subsystems
VTT LDO with IOCP	0.95A minimum current limit - sustains DDR termination under worst-case sink/source transients per JEDEC specification
Integrated 3.3V/5V LDOs	LDO3P3 (40mA) and LDO5P0 (180mA) - supply auxiliary system logic without requiring discrete regulators
Thermal Monitoring	THOT = 115°C ±5°C with 10°C hysteresis - triggers PROCHOT assertion to throttle SoC before die damage occurs

Applications

Ultrabook Power Subsystem	Tablet DDR Memory Management
Use Scenario: Primary power solution for Intel Apollo Lake-based ultrabooks with 3S Li-ion battery and 12V adapter input. IC Role / Device Role / Timing Role: PMIC provides sequenced, regulated rails (VNN, VCCGI, VDDQ, V1P8A, V1P24A, VCCRAM) and DDR termination (VTT) under Intel reference design timing constraints. Use Value: Integrates six VRs + VTT + LDOs + load switches in one 8mm × 8mm package - reduces board area by >40% vs. discrete solutions while meeting Intel VR13/VR14 compliance.	Use Scenario: LPDDR4 memory power and termination in fanless tablets operating from 2S–4S battery packs. IC Role / Device Role / Timing Role: TPS650940A0RSKR delivers 1.1V VDDQ (BUCK6), VTT = VDDQ/2, and V1P24A for LPDDR4 I/O, with precise tracking during DVS transitions. Use Value: OTP-configured VTT enablement and 1.1V BUCK6 ensure immediate LPDDR4 interoperability - eliminates firmware tuning for memory rail startup and refresh timing.
Industrial PC Power Sequencing	Connected Standby Platform
Use Scenario: Ruggedized industrial PC using Apollo Lake SoC in wide-temperature (-40°C to +85°C) environments. IC Role / Device Role / Timing Role: Manages cold-boot (PMICEN), S0/S3/S4 state transitions via SLP_S0B/SLP_S3B/SLP_S4B, and monitors die temperature (THERMTRIPB). Use Value: Built-in thermal shutdown (TCRIT = 145°C), UVLO thresholds (VSYS_UVLO_5V = 5.4V), and robust ESD rating (±1000V HBM) ensure reliability in uncontrolled power environments.	Use Scenario: Always-on, low-power IoT gateway with Intel Apollo Lake supporting Windows Connected Standby. IC Role / Device Role / Timing Role: Enters ultra-low-power state on SLP_S0B assertion, maintains VTT and always-on LDOs, and wakes on IRQB-triggered events. Use Value: 65µA shutdown current and programmable DVS slew rate (2.5–3.125 mV/µs) minimize leakage and prevent false wakeups during deep-sleep cycles.

Ultrabook Power Subsystem

Tablet DDR Memory Management

Use Scenario: Primary power solution for Intel Apollo Lake-based ultrabooks with 3S Li-ion battery and 12V adapter input.

IC Role / Device Role / Timing Role: PMIC provides sequenced, regulated rails (VNN, VCCGI, VDDQ, V1P8A, V1P24A, VCCRAM) and DDR termination (VTT) under Intel reference design timing constraints.

Use Value: Integrates six VRs + VTT + LDOs + load switches in one 8mm × 8mm package - reduces board area by >40% vs. discrete solutions while meeting Intel VR13/VR14 compliance.

Use Scenario: LPDDR4 memory power and termination in fanless tablets operating from 2S–4S battery packs.

IC Role / Device Role / Timing Role: TPS650940A0RSKR delivers 1.1V VDDQ (BUCK6), VTT = VDDQ/2, and V1P24A for LPDDR4 I/O, with precise tracking during DVS transitions.

Use Value: OTP-configured VTT enablement and 1.1V BUCK6 ensure immediate LPDDR4 interoperability - eliminates firmware tuning for memory rail startup and refresh timing.

Industrial PC Power Sequencing

Connected Standby Platform

Use Scenario: Ruggedized industrial PC using Apollo Lake SoC in wide-temperature (-40°C to +85°C) environments.

IC Role / Device Role / Timing Role: Manages cold-boot (PMICEN), S0/S3/S4 state transitions via SLP_S0B/SLP_S3B/SLP_S4B, and monitors die temperature (THERMTRIPB).

Use Value: Built-in thermal shutdown (TCRIT = 145°C), UVLO thresholds (VSYS_UVLO_5V = 5.4V), and robust ESD rating (±1000V HBM) ensure reliability in uncontrolled power environments.

Use Scenario: Always-on, low-power IoT gateway with Intel Apollo Lake supporting Windows Connected Standby.

IC Role / Device Role / Timing Role: Enters ultra-low-power state on SLP_S0B assertion, maintains VTT and always-on LDOs, and wakes on IRQB-triggered events.

Use Value: 65µA shutdown current and programmable DVS slew rate (2.5–3.125 mV/µs) minimize leakage and prevent false wakeups during deep-sleep cycles.

Equivalent & Alternatives

The following parts are listed as comparable options for similar PMIC applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
TPS650941RSKR	OTP config: LPDDR3 support, VTT enabled, BUCK6 = 1.2V, SLP_S3B controls SWB1_2	Targets Apollo Lake designs using LPDDR3 instead of LPDDR4; different memory interface timing and voltage	Select only when LPDDR3 memory is used and SLP_S3B-based switch control is required
TPS650944RSKR	OTP config: LPDDR4 support, VTT disabled, BUCK6 = 1.1V, SWA1_EN pin function (not LDOLS_EN)	Omits VTT LDO - suitable for non-DDR memory interfaces or external termination solutions	Choose when VTT is handled externally or not needed; verify SWA1_EN pin usage matches system enable logic

Compared with TPS650940A0RSKR, TPS650941RSKR supports LPDDR3 at 1.2V and uses SLP_S3B for load-switch control, while TPS650944RSKR removes VTT but retains LPDDR4 compatibility - making each variant mutually exclusive for specific memory architecture and power-state coordination requirements.

Availability

TPS650940A0RSKR is available at Aetrix Electronics and suitable for ultrabooks, tablets, and industrial PCs requiring stable component supply, Intel Apollo Lake platform compliance, and LPDDR4 memory power integration.

Supply support for TPS650940A0RSKR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of experience in high-reliability, high-efficiency power solutions.

The TPS65094x family is engineered specifically for Intel Atom™ and Apollo Lake platforms, delivering integrated, OTP-configurable power management to reduce design complexity and accelerate time-to-market for mobile and embedded computing systems.

FAQ

What is the OTP configuration of TPS650940A0RSKR?

The TPS650940A0RSKR is factory-programmed as the TPS650940 variant: DEVICEID = 0x08, supporting LPDDR4 memory, enabling VTT, setting BUCK6 default to 1.1V, and configuring SWB1_2 to respond to SLP_S4B. This OTP cannot be modified in-circuit and defines all memory interface and power-state behaviors of the TPS650940A0RSKR.

Does TPS650940A0RSKR support DDR3L or DDR4 memory?

No. TPS650940A0RSKR's OTP configuration explicitly supports LPDDR4 only. It does not support DDR3L or DDR4 memory interfaces - those require other variants such as TPS650942 (DDR3L) or TPS650947 (DDR3L). Using TPS650940A0RSKR with DDR3L/DDR4 would result in incorrect BUCK6 voltage and missing VTT functionality.

What is the maximum output current capability of BUCK2 in TPS650940A0RSKR?

TPS650940A0RSKR supports up to 21A output current on BUCK2 (VCCGI rail) using external high-side and low-side FETs. This rating assumes proper thermal design (R_θJA ≤ 25.8°C/W), correct ILIM2 resistor selection, and adherence to recommended inductor (0.47µH) and output capacitance (220µF) values per the datasheet.

How is dynamic voltage scaling implemented on TPS650940A0RSKR?

TPS650940A0RSKR implements DVS on BUCK1 and BUCK2 via I²C register writes to VID[6:0] fields, enabling 10mV-step adjustments from 0.5V to 1.45V. The DVS slew rate is fixed at 2.5–3.125 mV/µs, ensuring controlled transitions that avoid SoC reset or instability during voltage changes.

Is the thermal pad of TPS650940A0RSKR electrically connected internally?

Yes. The thermal pad of TPS650940A0RSKR is internally connected to PGND and must be soldered to the PCB's power ground plane using multiple thermal vias. Failure to connect the pad compromises both thermal performance (increasing R_θJA) and electrical integrity of power return paths for all buck regulators.

TPS650940A0RSKR Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: D-CAP2™

Package/Case:: 64-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Applications:: Controller/Converter, Mobile PCs

Voltage - Input:: 5.6V ~ 21V

Number of Outputs:: 12

Voltage - Output:: Multiple

Operating Temperature:: -40°C ~ 85°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 64-VQFN (8x8)

TPS650940A0RSKR FAQ

1.How can I place an order for TPS650940A0RSKR through Aetrix?

Please submit a Request for Quotation (RFQ) for TPS650940A0RSKR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for TPS650940A0RSKR reliable?

The price and inventory of TPS650940A0RSKR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS650940A0RSKR is usually 5 days.

3.What payment methods are accepted for TPS650940A0RSKR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS650940A0RSKR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for TPS650940A0RSKR?

TPS650940A0RSKR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your TPS650940A0RSKR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for TPS650940A0RSKR?

For technical support, including TPS650940A0RSKR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS650940A0RSKR requirements.

6.How does Aetrix verify that TPS650940A0RSKR is sourced from the original manufacturer or authorized distributors?

All TPS650940A0RSKR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS650940A0RSKR meets industry standards.

7.What is the process for return or replacement of TPS650940A0RSKR?

All TPS650940A0RSKR units undergo pre-shipment inspection (PSI). If there is an issue with TPS650940A0RSKR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The TPS650940A0RSKR part is unused and in its original packaging.

Return procedure for TPS650940A0RSKR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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