Texas Instruments TPS650940A0RSKT

Overview

TPS650940A0RSKT from Texas Instruments is a power-management IC (PMIC) designed for Intel™ Apollo Lake platforms, integrating six synchronous buck regulators (three controllers + three converters), three adjustable LDOs, one VTT LDO, and three load switches. It delivers 5A/7A/21A output capability across BUCK1/BUCK6/BUCK2, supports I²C dynamic voltage scaling from 0.5V to 1.45V in 10mV steps, and targets DDR3L memory systems in ultrabooks and industrial PCs.

For engineers reviewing the TPS650940A0RSKT datasheet, TPS650940A0RSKT pinout, TPS650940A0RSKT application, or TPS650940A0RSKT equivalent, key selection criteria include OTP-programmed VDDQ default voltage (1.1V), VTT disable capability, SLP_S3B/S4B-controlled SWB1_2 behavior, and compatibility with Intel reference designs for Apollo Lake SoCs.

Technical Context

The TPS650940A0RSKT implements D-CAP2™ topology for BUCK1/BUCK2/BUCK6 controllers-enabling fast transient response without external compensation-and dcs-control for BUCK3/BUCK4/BUCK5 converters, supporting forced PWM mode per OTP configuration. Its I²C interface (0x5E address) operates up to 1 MHz and manages rail sequencing, DVS, and fault reporting via IRQB, PROCHOT, and PCH_PWROK signals.

OTP programming defines critical system-level behaviors: BUCK6 defaults to 1.1V, VTT is disabled, SWB1_2 is controlled by SLP_S4B (not SLP_S3B), and LDOA1 is not always-on. Pin 14 functions as LDOLS_EN-not SWA1_EN-enabling coordinated startup of LDOA2/LDOA3/SWA1 under host control or direct assertion.

Key Specifications

Pinout & Package

TPS650940A0RSKT uses an 8mm × 8mm, 64-pin VQFN package (RSK) with exposed thermal pad soldered to PCB ground plane for optimal thermal performance. Pin assignment follows TI's standardized Apollo Lake PMIC layout, with dedicated feedback (FBVOUTx), gate drive (DRVHx/DRVLx), bootstrap (BOOTx), and sense (PGNDSNSx) pins for each controller.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PMIC applications.

Compared with TPS650940A0RSKT, TPS650941RSKT adds VTT support but removes VTT disable flexibility, while TPS650944RSKT trades LDOA1 sequencing control for guaranteed PWM operation-making TPS650940A0RSKT optimal for DDR3L systems prioritizing OTP simplicity and minimal rail count.

Availability

TPS650940A0RSKT is available at Aetrix Electronics and suitable for ultrabooks, industrial PCs, and Apollo Lake-based tablets requiring stable component supply, long-term lifecycle support, and Intel platform validation.

Supply support for TPS650940A0RSKT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog and embedded processing technologies, with leadership in power management ICs for computing, industrial, and automotive markets.

The TPS65094 family is engineered specifically for Intel Apollo Lake SoCs, delivering integrated, OTP-configurable power solutions that replace multiple discrete regulators while meeting Intel VR reference design timing, sequencing, and efficiency requirements.

FAQ

What is the default VDDQ output voltage programmed in TPS650940A0RSKT?

The TPS650940A0RSKT has OTP-programmed BUCK6 (VDDQ) default voltage set to 1.1 V, matching JEDEC DDR3L specifications. This value is fixed at manufacturing and cannot be altered via I²C registers. The TPS650940A0RSKT datasheet confirms this in Table 4-1 under "BUCK6 Voltage" and specifies it as a hard-coded OTP option distinct from other variants like TPS650941 (1.2 V) or TPS650942 (1.35 V).

Does TPS650940A0RSKT support VTT termination for DDR memory?

No, TPS650940A0RSKT has VTT disabled per its OTP configuration, as documented in Table 4-1 of the datasheet. This makes it suitable for DDR3L or LPDDR4 systems where VTT is not required. If VTT sourcing/sinking is needed-for example, in LPDDR3 implementations-TPS650941RSKT or TPS650942RSKT must be selected instead, as those variants have VTT enabled and higher IOCP ratings.

How is the SWB1_2 load switch controlled on TPS650940A0RSKT?

On TPS650940A0RSKT, the SWB1_2 load switch is controlled exclusively by the SLP_S4B signal, as defined by its OTP mapping (Table 4-1). It is not responsive to SLP_S3B. This behavior ensures rail shutdown aligns with Intel S4 (hibernate) state entry/exit, distinguishing it from variants like TPS650942RSKT where SWB1_2 is tied to SLP_S3B for S3 (suspend-to-RAM) control.

What is the function of Pin 14 on TPS650940A0RSKT?

Pin 14 on TPS650940A0RSKT is configured as LDOLS_EN per its OTP setting, enabling simultaneous control of LDOA2, LDOA3, and SWA1. It is not SWA1_EN. When asserted high, it powers up all three resources; when deasserted low, they shut down. This differs from TPS650944RSKT, where Pin 14 serves as SWA1_EN only-highlighting OTP-driven functional divergence within the TPS65094x family.

What I²C address does TPS650940A0RSKT use for communication?

TPS650940A0RSKT uses I²C device address 0x5E, consistent across all TPS65094x variants. This 7-bit address supports Standard Mode (100 kHz), Fast Mode (400 kHz), and Fast Mode Plus (1 MHz), enabling flexible host-controller interfacing. The address is hardware-fixed and not software-configurable, ensuring deterministic bus arbitration in multi-PMIC systems.