Texas Instruments TPS650944A0RSKT
- Part No.:
- TPS650944A0RSKT
- Manufacturer:
- Texas Instruments
- Category:
- Special Purpose Regulators
- Package:
- 64-VFQFN Exposed Pad
- Datasheet:
-
TPS650944A0RSKT.pdf
- Description:
- IC REG CTRLR/CONV 12OUT 64VQFN
- Quantity:
- Payment:

- Shipping:

Inventory:239
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Product details
Overview
TPS650944A0RSKT from Texas Instruments is a highly integrated power-management IC (PMIC) designed for Intel™ Apollo Lake platforms, delivering six synchronous buck regulators (three controllers + three converters), three adjustable LDOs, a VTT LDO for DDR termination, and three slew-rate-controlled load switches. It supports dynamic voltage scaling (DVS) on BUCK1 and BUCK2, delivers up to 21A output on BUCK2 (VCCGI), and operates from 5.6V–21V input for battery or wall-powered mobile computing systems.
For engineers reviewing the TPS650944A0RSKT datasheet, TPS650944A0RSKT pinout, TPS650944A0RSKT application, or TPS650944A0RSKT equivalent, this page provides verified functional identity, OTP-specific configuration (LPDDR4 support, VTT disabled, LDOA1 always-on at 1.8V), validated pin mapping for RSK 64-pin VQFN, and confirmed alternative options for Intel platform PMIC replacement scenarios.
Technical Context
The TPS650944A0RSKT implements D-CAP2™ topology for BUCK1/BUCK2/BUCK6 controllers (supporting external FETs) and DCS-Control™ for BUCK3/BUCK4/BUCK5 converters (integrated FETs), enabling high efficiency across light-to-heavy loads. Its I²C interface (address 0x5E) enables full rail control-including 10-mV-step DVS, OTP-programmed BUCK6 default (1.1V), and configurable power sequencing via SLP_S0B/SLP_S3B/SLP_S4B inputs.
OTP configuration TPS650944 fixes key behavior: VTT disabled, LDOA1 always-on at 1.8V default, LDOA2/LDOA3 defaults at 0.7V, SWB1_2 controlled by SLP_S4B, and BUCK3–BUCK5 operating in Auto mode-distinguishing it from TPS650945/TPS650947 which mandate Forced PWM for noise-sensitive applications.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 5.6V–21V for main rails (BUCK1/2/6); 4.5V–5.5V for BUCK3/4/5 - supports 2S–4S Li-ion and 12V wall adapters |
| Output Current Capability | 21A on BUCK2 (VCCGI), 7A on BUCK6 (VDDQ), 5A on BUCK1 (VNN), 3A on BUCK3 (VCCRAM), 2A each on BUCK4/V1P8A & BUCK5/V1P24A |
| DVS Resolution & Range | 10mV steps from 0.5V–1.45V on BUCK1 and BUCK2 - enables fine-grained Intel processor core voltage tuning |
| I²C Interface Speed | Supports Standard (100kHz), Fast (400kHz), and Fast Mode Plus (1MHz) - allows rapid rail reconfiguration during state transitions |
| OTP-Defined Configuration | TPS650944: LPDDR4 support, VTT disabled, LDOA1 always-on at 1.8V, SWB1_2 tied to SLP_S4B, BUCK3–5 in Auto mode |
| Thermal Performance | RθJA = 25.8°C/W (RSK 64-pin VQFN); junction temp rated to 125°C - requires thermal pad connection to PCB ground plane |
| Package | VQFN-64 (RSK), 8.0mm × 8.0mm body with exposed thermal pad - optimized for compact mobile PCB layouts |
Pinout & Package
TPS650944A0RSKT uses an 8mm × 8mm, 64-pin VQFN package (RSK) with exposed thermal pad requiring connection to system power ground plane for thermal and electrical performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| FBGND2 / FBVOUT2 | Remote feedback sense pair for BUCK2 | Connects to SoC VCCGI VSS/VCC SENSE lines - enables accurate remote voltage regulation at processor die |
| DRVH2 / DRVL2 / BOOT2 / SW2 | BUCK2 gate driver interface | Drives external high-side/low-side FETs; BOOT2 requires 100nF ceramic cap to SW2 - defines VCCGI switching stage |
| ILIM2 | BUCK2 current limit set | Resistor-to-ground sets valley current limit of external low-side FET - critical for overcurrent protection calibration |
| LDOA1 / LDOA2 / LDOA3 | Adjustable LDO outputs | I²C-selectable 1.35–3.3V (LDOA1, always-on), 0.7–1.5V (LDOA2/A3) - powers auxiliary platform rails like eMMC or sensors |
| SWA1 / SWB1 / SWB2 | Load switch outputs | Each delivers ≤400mA with <96mΩ RDS(on) at 1.8V - used for sequenced peripheral power enable (e.g., USB, display) |
| SLP_S0B / SLP_S3B / SLP_S4B | Power state control inputs | Directly control PMIC entry/exit from Connected Standby (S0iX), S3, and S4 states - synchronized with Intel PCH |
| DATA / CLK / PMICEN / IRQB | I²C interface & control | I²C address 0x5E; PMICEN initiates cold boot; IRQB signals faults (thermal, UVLO, OCP) - enables full system-level power management |
Key Features
| Feature | Design Value |
|---|---|
| D-CAP2™ Buck Controllers (BUCK1/2/6) | Enables fast transient response and stable operation without external compensation - reduces design cycle time for high-current CPU/GPU rails |
| DCS-Control™ Buck Converters (BUCK3/4/5) | Integrates power FETs and supports seamless transition between PWM and PFM modes - improves light-load efficiency for memory and I/O rails |
| OTP-Configured LPDDR4 Support | TPS650944 fixes BUCK6 output to 1.1V and disables VTT - matches LPDDR4 termination requirements without firmware override |
| LDOA1 Always-On at 1.8V | Guarantees continuous power to always-on domain peripherals (e.g., RTC, wake logic) - eliminates need for external bias rail |
| VQFN Thermal Pad Integration | Exposed pad with RθJB = 4.4°C/W enables direct heat transfer to PCB ground - sustains 21A BUCK2 operation under sustained load |
Applications
| Intel Apollo Lake Tablet Power System | Ultrabook DDR4 Memory Subsystem |
|---|---|
Use Scenario: Compact tablet design powered by 3S Li-ion battery (11.1V nominal) with LPDDR4 memory and Intel Atom x5/x7 processor. IC Role / Device Role / Timing Role: Central PMIC providing all core, SoC, memory, and peripheral rails with Intel-specified sequencing and DVS coordination. Use Value: Single-chip integration eliminates discrete VRMs and LDOs, reducing BOM count by >12 components while meeting Apollo Lake's strict power-state timing (S0i3/S3/S4). |
Use Scenario: Fanless ultrabook requiring low-noise, high-efficiency DDR4 termination and VDDQ regulation. IC Role / Device Role / Timing Role: Generates VDDQ (1.1V) via BUCK6 and supplies VTT (0.55V) - but TPS650944 disables VTT, so VTT is sourced externally per LPDDR4 spec. Use Value: OTP-configured 1.1V BUCK6 output and Auto-mode BUCK3–5 minimize EMI during light-load operation - critical for audio/video subsystems. |
| Industrial Mobile PC Platform | IoT Gateway with Extended Temp Range |
Use Scenario: Ruggedized mobile PC for warehouse automation, operating from 12V wall adapter and 2S/3S battery backup. IC Role / Device Role / Timing Role: Manages dual-input NVDC architecture, prioritizing wall power while seamlessly transitioning to battery during outages. Use Value: Wide 5.6V–21V input range and –40°C to +85°C ambient rating ensure reliable operation across industrial power environments. |
Use Scenario: Edge IoT gateway with Intel Apollo Lake SoC, cellular modem, and multiple sensor interfaces operating in uncontrolled ambient conditions. IC Role / Device Role / Timing Role: Powers SoC cores (BUCK1/2), LPDDR4 (BUCK6), I/O rails (BUCK3/4/5), and always-on peripherals (LDOA1) with thermal shutdown at 130°C (TCRIT). Use Value: Integrated thermal monitoring (THOT/TCRIT thresholds) and open-drain PROCHOT output enable SoC thermal throttling coordination - prevents thermal runaway. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multi-rail PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS650945RSKT | Forced PWM mode for BUCK3–5; VTT enabled; BUCK6 = 1.1V; DEVICEID = 0xDh | Required when low-noise, fixed-frequency operation needed for sensitive analog/audio circuits - avoids Auto-mode frequency modulation | Select TPS650945RSKT only if BUCK3–5 noise immunity is critical; not drop-in due to differing PWM control and VTT enable state |
| TPS650947RSKT | Forced PWM mode for BUCK3–5; VTT enabled; BUCK6 = 1.35V; DEVICEID = 0xFh | Matches DDR3L memory systems requiring 1.35V VDDQ and active VTT termination - incompatible with LPDDR4 | Choose TPS650947RSKT for DDR3L-based Apollo Lake designs; differs in OTP voltage, VTT status, and BUCK3–5 control mode |
Compared with TPS650944A0RSKT, TPS650945RSKT and TPS650947RSKT both enforce Forced PWM on BUCK3–5 to suppress light-load frequency variation, but differ in VTT enablement and BUCK6 voltage - making them non-interchangeable without board-level and firmware validation.
Availability
TPS650944A0RSKT is available at Aetrix Electronics and suitable for Intel Apollo Lake tablets, ultrabooks, and industrial mobile PCs requiring stable component supply, long-term lifecycle support, and guaranteed OTP configuration consistency.
Supply support for TPS650944A0RSKT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management solutions, with decades of collaboration on Intel platform reference designs.
The TPS65094 family was developed specifically for Intel Apollo Lake processors, integrating all required power rails, sequencing, and Intel-specified DVS/thermal interfaces into a single VQFN package for space-constrained mobile computing.
FAQ
What is the OTP configuration of TPS650944A0RSKT?
The TPS650944A0RSKT is factory-programmed with OTP settings for LPDDR4 memory support: BUCK6 default voltage is 1.1V, VTT is disabled, LDOA1 is always-on at 1.8V, LDOA2/LDOA3 defaults are 0.7V, and SWB1_2 is controlled by SLP_S4B. These values are fixed and cannot be altered in-circuit - they define the device's functional identity within the TPS65094x family.
Does TPS650944A0RSKT support DDR4 memory termination?
No, TPS650944A0RSKT does not support DDR4 memory termination because its OTP disables the VTT LDO function. While it provides BUCK6 at 1.1V for LPDDR4 VDDQ, DDR4 requires active VTT regulation at VDDQ/2 - a capability present in TPS650945RSKT and TPS650947RSKT but explicitly disabled in TPS650944A0RSKT per its OTP map.
What is the maximum output current capability of BUCK2 in TPS650944A0RSKT?
TPS650944A0RSKT supports up to 21A output current on BUCK2 (VCCGI) using external high-side and low-side FETs. This rating assumes proper thermal design (including thermal pad connection), appropriate external inductor (0.376–0.564µH), and output capacitance (≥220µF), as specified in the datasheet's electrical characteristics and layout guidelines.
How is dynamic voltage scaling implemented on TPS650944A0RSKT?
TPS650944A0RSKT implements DVS on BUCK1 and BUCK2 via I²C register writes to VID[6:0] fields, enabling 10mV output voltage steps from 0.5V to 1.45V. The slew rate is fixed at 2.5–3.125mV/µs, ensuring controlled transitions during Intel processor state changes such as Connected Standby entry/exit.
What package type and thermal requirements apply to TPS650944A0RSKT?
TPS650944A0RSKT uses the RSK 64-pin VQFN package (8.0mm × 8.0mm) with an exposed thermal pad that must be soldered to the PCB's internal or bottom-layer ground plane using multiple thermal vias. Its RθJA is 25.8°C/W; failure to implement proper thermal relief risks exceeding the 125°C max junction temperature under sustained 21A BUCK2 load.
TPS650944A0RSKT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- D-CAP2™
- Package/Case:
- 64-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- Controller/Converter, Mobile PCs
- Voltage - Input:
- 5.6V ~ 21V
- Number of Outputs:
- 12
- Voltage - Output:
- Multiple
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 64-VQFN (8x8)
TPS650944A0RSKT FAQ
1.How can I place an order for TPS650944A0RSKT through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS650944A0RSKT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS650944A0RSKT reliable?
The price and inventory of TPS650944A0RSKT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS650944A0RSKT is usually 5 days.
3.What payment methods are accepted for TPS650944A0RSKT?
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TPS650944A0RSKT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS650944A0RSKT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS650944A0RSKT?
For technical support, including TPS650944A0RSKT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS650944A0RSKT requirements.
6.How does Aetrix verify that TPS650944A0RSKT is sourced from the original manufacturer or authorized distributors?
All TPS650944A0RSKT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS650944A0RSKT meets industry standards.
7.What is the process for return or replacement of TPS650944A0RSKT?
All TPS650944A0RSKT units undergo pre-shipment inspection (PSI). If there is an issue with TPS650944A0RSKT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS650944A0RSKT part is unused and in its original packaging.
Return procedure for TPS650944A0RSKT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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