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Texas Instruments TPS650945A0RSKR
- Part No.:
- TPS650945A0RSKR
- Manufacturer:
- Texas Instruments
- Category:
- Special Purpose Regulators
- Package:
- 64-VFQFN Exposed Pad
- Datasheet:
-
TPS650945A0RSKR.pdf
- Description:
- IC PWR MGMT SWITCHING REGULATOR
- Quantity:
- Payment:
- Shipping:
Inventory:4,553
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Product details
Overview
TPS650945A0RSKR from Texas Instruments is a power-management IC (PMIC) designed for Intel™ Apollo Lake platforms, integrating six synchronous buck regulators (three controllers + three converters), three adjustable LDOs, VTT termination, and three slew-controlled load switches. It delivers 5A/7A/21A output capability on BUCK1/BUCK6/BUCK2, supports I²C dynamic voltage scaling from 0.5V to 1.45V in 10mV steps, and operates from 5.6V–21V input for battery or wall-powered mobile computing systems.
For engineers reviewing the TPS650945A0RSKR datasheet, TPS650945A0RSKR pinout, TPS650945A0RSKR application, or TPS650945A0RSKR equivalent, this page provides verified technical context, validated pin functions, confirmed OTP-specific behavior (LPDDR4 support, VTT enabled, Forced PWM mode for BUCK3–BUCK5), and real-world design implications for Intel platform power sequencing and DDR memory rail integrity.
Technical Context
The TPS650945A0RSKR implements D-CAP2™ topology for BUCK1, BUCK2, and BUCK6 - high-current step-down controllers driving external FETs - and dcs-control topology for BUCK3, BUCK4, and BUCK5 - integrated-FET synchronous converters with 3A/2A/2A output capability. All six VRs are coordinated by hardware-based power-up sequence logic compliant with Intel reference designs.
This variant is OTP-programmed for LPDDR4 memory interface (per Table 4-1), enables VTT LDO (not disabled), sets BUCK6 default output to 1.1V, configures BUCK3–BUCK5 in Forced PWM mode to suppress light-load frequency switching noise, and assigns Pin 14 as LDOLS_EN (enabling LDOA2/LDOA3/SWA1 together). Its thermal pad (RSK package) requires direct PCB ground connection for junction-to-board RθJB = 4.4°C/W performance.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VIN Range | 5.6V–21V for BUCK1/BUCK2/BUCK6 controllers; 4.5V–5.5V for BUCK3/BUCK4/BUCK5 converters - supports 2S–4S Li-ion battery packs and 12V wall adapters. |
| Output Current | 5A (BUCK1/VNN), 21A (BUCK2/VCCGI), 7A (BUCK6/VDDQ), 3A (BUCK3/VCCRAM), 2A each (BUCK4/V1P8A & BUCK5/V1P24A) - matches Intel Apollo Lake SoC rail requirements. |
| DVS Resolution | 10mV steps across 0.5V–1.45V range for BUCK1 and BUCK2 - enables fine-grained connected standby efficiency tuning per Intel specification. |
| I²C Interface | Address 0x5E; supports Standard (100kHz), Fast (400kHz), and Fast Mode Plus (1MHz) - allows EC/SoC real-time rail reconfiguration without firmware overhead. |
| OTP Configuration | TPS650945 variant: LPDDR4 support, VTT enabled, BUCK6 = 1.1V, BUCK3–BUCK5 in Forced PWM, Pin 14 = LDOLS_EN, LDOA1 default = 3.3V - fixed at factory, non-reprogrammable. |
| Thermal Performance | RθJA = 25.8°C/W, RθJB = 4.4°C/W - requires thermal pad soldered to PCB ground plane with multiple vias for sustained 21A operation. |
| Package | VQFN-64 (RSK), 8.0mm × 8.0mm, single-row layout with exposed thermal pad - optimized for compact mobile PCB routing and thermal dissipation. |
Pinout & Package
VQFN-64 (RSK) package with 8.0mm × 8.0mm body and exposed thermal pad requiring connection to system power ground plane via multiple vias for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| FBGND2, FBVOUT2 | Remote feedback sense pair for BUCK2 | Connects to VCCGI VSS/VCC SENSE lines from SoC - enables accurate regulation under high-current transient loads (up to 21A). |
| DRVH2, DRVL2, SW2, BOOT2 | BUCK2 gate driver and switch node | Drives external high-side/low-side FETs; BOOT2 requires 100nF ceramic cap to SW2 - supports >20A peak current with low RDS(on) FET selection. |
| LX3, PVIN3, FB3 | BUCK3 converter switch node, input, feedback | Integrated 3A converter for VCCRAM; LX3 connects to 0.47µH inductor (<50mΩ DCR); PVIN3 bypassed with 10µF ceramic cap - optimized for LPDDR4 memory supply stability. |
| LDOA1, LDOA2, LDOA3 | Adjustable LDO outputs | LDOA1: 1.35–3.3V @ 200mA; LDOA2/LDOA3: 0.7–1.5V @ 600mA each - I²C-selectable, used for auxiliary platform rails (e.g., PCIe, USB PHY, sensor interfaces). |
| VTT, VTTFB, PVINVTT | VTT DDR termination LDO | VTT = VDDQ/2; VTTFB connects to DDR VTT capacitor bank; PVINVTT sourced from VDDQ - provides precise, low-noise termination for LPDDR4 signaling integrity. |
| PMICEN, SLP_S0B, SLP_S3B, SLP_S4B | Power state control inputs | Hardware-driven sequencing: PMICEN initiates cold boot; SLP_S0B enters/exits Connected Standby; SLP_S3B/SLP_S4B transition between S3/S4 states - aligns with Intel ACPI power state definitions. |
| DATA, CLK, IRQB, PCH_PWROK | I²C interface and status outputs | Open-drain IRQB signals fault conditions (thermal, overcurrent); PCH_PWROK indicates global power-good status - enables SoC-level power management coordination. |
Key Features
| Feature | Design Value |
|---|---|
| D-CAP2™ Controllers | BUCK1/BUCK2/BUCK6 use D-CAP2™ for fast transient response and no external compensation - reduces component count and improves load-step immunity for CPU/GPU core rails. |
| dcs-Control Converters | BUCK3/BUCK4/BUCK5 employ dcs-control for tight DC accuracy and ultra-low ripple - critical for noise-sensitive LPDDR4 memory and analog subsystems. |
| Forced PWM Mode (OTP) | BUCK3–BUCK5 locked in Forced PWM (not Auto mode) - eliminates audible switching noise and prevents voltage undershoot/overshoot during light-load transitions in LPDDR4 applications. |
| VTT LDO with Remote Sense | VTT output regulated to exact VDDQ/2 with VTTFB remote feedback - maintains DDR signal integrity across board trace impedance variations and temperature drift. |
| Hardware Sequencing Logic | Internal state machine sequences all 6 VRs, VTT, and LDOs per Intel reference timing - eliminates need for external CPLD/FPGA sequencing control and reduces BOM cost. |
Applications
| Intel Apollo Lake Tablet | Ultrabook Platform Power |
|---|---|
|
Use Scenario: 12.9-inch tablet powered by 3S Li-ion battery (11.1V nominal) with LPDDR4 memory and dual-display output. IC Role / Device Role / Timing Role: Primary PMIC managing all SoC core, memory, and I/O rails; executes Intel-defined power-on reset and S0→S3→S4 state transitions. Use Value: Enables <100ms wake-from-sleep latency and <50mV VCCGI load transient deviation at 21A step - meeting Intel Connected Standby timing and voltage tolerance specs. |
Use Scenario: Fanless ultrabook using 12V wall adapter, targeting 15W TDP and 12-hour battery life with LPDDR4-3200 memory. IC Role / Device Role / Timing Role: Single-chip power solution delivering VNN (CPU), VCCGI (GPU), VDDQ (memory), VCCRAM (LPDDR4), and V1P8A/V1P24A (I/O) rails with synchronized sequencing. Use Value: Reduces total power solution footprint by 35% vs discrete VRs; Forced PWM mode ensures stable VCCRAM under variable memory bandwidth loads without audible coil whine. |
| Industrial IoT Gateway | Mobile Internet Device (MID) |
|
Use Scenario: Ruggedized edge gateway operating in –40°C to +85°C ambient, supporting LTE, Wi-Fi, and dual Ethernet with Intel Apollo Lake SoC. IC Role / Device Role / Timing Role: Robust power manager handling wide-input (5.6V–21V) battery/adapter operation, thermal shutdown (THOT = 115°C), and DDR3L/LPDDR4 compatibility via OTP selection. Use Value: Maintains ±2% VOUT accuracy across full temperature range and supports 130°C critical thermal shutdown - ensuring reliable operation in uncontrolled environments. |
Use Scenario: Portable 7-inch MID with 2S Li-ion battery (7.4V), capacitive touchscreen, and Android OS optimized for Intel architecture. IC Role / Device Role / Timing Role: Integrated power hub supplying VNN, VCCGI, VDDQ, VCCRAM, and auxiliary LDOs while enabling rapid suspend/resume cycles via SLP_S0B hardware control. Use Value: Achieves <20µA shutdown current (ISD = 65µA typical) and supports 10mV DVS steps - extending battery runtime and enabling precise CPU DVFS for thermal-aware performance scaling. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS650944RSKR | OTP-configured for LPDDR4 but disables VTT; BUCK3–BUCK5 in Auto mode (not Forced PWM); Pin 14 = SWA1_EN (not LDOLS_EN). | Suitable for LPDDR4 systems where VTT termination is handled externally or not required; Auto mode may cause light-load noise in memory rails. | Select only if VTT is omitted and noise sensitivity is low; verify BUCK3–BUCK5 stability under light load before adoption. |
| TPS650947RSKR | OTP-configured for DDR3L (not LPDDR4); VTT enabled; BUCK6 default = 1.35V (not 1.1V); same Forced PWM mode for BUCK3–BUCK5. | Targeted at legacy DDR3L-based Apollo Lake designs; incompatible with LPDDR4 memory timing and voltage requirements. | Use only for DDR3L platforms; mismatched BUCK6 voltage and memory interface will prevent LPDDR4 initialization. |
Compared with TPS650944RSKR and TPS650947RSKR, the TPS650945A0RSKR uniquely combines LPDDR4 support, enabled VTT, 1.1V BUCK6 default, and Forced PWM for BUCK3–BUCK5 - making it the sole OTP variant qualified for noise-critical, high-bandwidth LPDDR4 mobile computing applications.
Availability
TPS650945A0RSKR is available at Aetrix Electronics and suitable for Intel Apollo Lake tablets, ultrabooks, and industrial IoT gateways requiring stable component supply, long-term lifecycle support, and guaranteed OTP configuration consistency.
Supply support for TPS650945A0RSKR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of experience in Intel platform reference designs.
The TPS65094 family was engineered specifically for Intel Apollo Lake SoCs - consolidating power sequencing, DDR memory termination, and multi-rail conversion into a single 8mm × 8mm VQFN package to minimize footprint and cost in space-constrained mobile devices.
FAQ
What is the OTP configuration of TPS650945A0RSKR?
The TPS650945A0RSKR is factory-programmed with OTP code 'Dh' (per Table 4-1), enabling LPDDR4 memory interface support, VTT LDO activation, BUCK6 default output set to 1.1V, BUCK3–BUCK5 forced into PWM mode (not Auto), and Pin 14 configured as LDOLS_EN. This configuration is permanent and cannot be altered in-system.
Does TPS650945A0RSKR support dynamic voltage scaling for all buck regulators?
TPS650945A0RSKR supports I²C-based dynamic voltage scaling (DVS) only for BUCK1 (VNN) and BUCK2 (VCCGI), with 10mV resolution across 0.5V–1.45V. BUCK3–BUCK5 operate at fixed I²C-programmable voltages (e.g., VCCRAM at 1.1V) and do not support real-time DVS during operation.
Why is Forced PWM mode critical for BUCK3–BUCK5 in TPS650945A0RSKR?
Forced PWM mode in TPS650945A0RSKR prevents abnormal frequency switching and minimizes noise at light loads - a known issue in Auto mode that can cause voltage undershoot/overshoot and potential system shutdown. This is essential for stable LPDDR4 memory operation where rail noise directly impacts data integrity.
How is VTT regulation implemented in TPS650945A0RSKR?
TPS650945A0RSKR integrates a dedicated VTT LDO with remote sensing (VTTFB pin) referenced to VDDQ. The VTT output is precisely regulated to VDDQ/2, and PVINVTT must be connected to the VDDQ rail. This ensures accurate DDR termination across temperature and load variations without external components.
What thermal management is required for TPS650945A0RSKR at 21A load?
At full 21A BUCK2 output, TPS650945A0RSKR requires its exposed thermal pad to be soldered to a solid PCB ground plane using ≥6 thermal vias (0.3mm diameter) to achieve RθJB = 4.4°C/W. Without this, junction temperature may exceed 125°C under sustained load, triggering THOT thermal shutdown.
TPS650945A0RSKR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 64-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- Controller/Converter, Mobile PCs
- Voltage - Input:
- 5.6V ~ 21V
- Number of Outputs:
- 12
- Voltage - Output:
- Multiple
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 64-VQFN (8x8)
TPS650945A0RSKR FAQ
1.How can I place an order for TPS650945A0RSKR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS650945A0RSKR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS650945A0RSKR reliable?
The price and inventory of TPS650945A0RSKR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS650945A0RSKR is usually 5 days.
3.What payment methods are accepted for TPS650945A0RSKR?
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4.How is shipping managed for TPS650945A0RSKR?
TPS650945A0RSKR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS650945A0RSKR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS650945A0RSKR?
For technical support, including TPS650945A0RSKR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS650945A0RSKR requirements.
6.How does Aetrix verify that TPS650945A0RSKR is sourced from the original manufacturer or authorized distributors?
All TPS650945A0RSKR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS650945A0RSKR meets industry standards.
7.What is the process for return or replacement of TPS650945A0RSKR?
All TPS650945A0RSKR units undergo pre-shipment inspection (PSI). If there is an issue with TPS650945A0RSKR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS650945A0RSKR part is unused and in its original packaging.
Return procedure for TPS650945A0RSKR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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