My Inquiry
My Account
Texas Instruments TPS650945A0RSKT
- Part No.:
- TPS650945A0RSKT
- Manufacturer:
- Texas Instruments
- Category:
- Special Purpose Regulators
- Package:
- 64-VFQFN Exposed Pad
- Datasheet:
-
TPS650945A0RSKT.pdf
- Description:
- IC PWR MGMT SWITCHING REGULATOR
- Quantity:
- Payment:
- Shipping:
Inventory:250
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TPS650945A0RSKT from Texas Instruments is a power-management IC (PMIC) designed for Intel™ Apollo Lake platforms, integrating six synchronous buck regulators (three controllers + three converters), three adjustable LDOs, VTT termination, and three load switches. It delivers 5A/7A/21A output capability across BUCK1/BUCK6/BUCK2, supports I²C dynamic voltage scaling (0.5V–1.45V in 10mV steps), and operates from 5.6V–21V input for battery or wall-powered mobile computing systems.
For engineers reviewing the TPS650945A0RSKT datasheet, TPS650945A0RSKT pinout, TPS650945A0RSKT application, or TPS650945A0RSKT equivalent, this page provides verified technical context, validated pin functions, confirmed OTP-specific behavior (LPDDR4 support, VTT disabled, Forced PWM mode for BUCK3–BUCK5), and real-world design implications for Intel platform power sequencing and DDR memory rail management.
Technical Context
The TPS650945A0RSKT implements D-CAP2™ topology for BUCK1/BUCK2/BUCK6 controllers driving external FETs, and dcs-control topology for BUCK3/BUCK4/BUCK5 converters with integrated FETs. Its OTP configuration fixes LPDDR4 compatibility, disables VTT, sets BUCK6 to 1.1V default, and forces PWM mode on BUCK3–BUCK5 to suppress light-load frequency switching noise - a critical requirement for stable DDR3L/LPDDR4 memory operation.
Power-up sequencing is hardware-controlled via SLP_S0B/SLP_S3B/SLP_S4B inputs, while I²C (address 0x5E, up to 1MHz) enables dynamic voltage scaling and rail enable/disable. The device integrates thermal monitoring (THOT = 115°C, TCRIT = 145°C), overcurrent protection per rail, and dedicated feedback paths (e.g., FBGND2/FBVOUT2 for remote sensing of VCCGI).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VIN Range | 5.6V–21V for BUCK1/BUCK2/BUCK6 controllers; 4.5V–5.5V for BUCK3/BUCK4/BUCK5 converters - supports dual-input architectures (battery + system rail). |
| Output Current | 5A (BUCK1/VNN), 21A (BUCK2/VCCGI), 7A (BUCK6/VDDQ), 3A (BUCK3/VCCRAM), 2A each (BUCK4/V1P8A & BUCK5/V1P24A) - matches Intel Apollo Lake SoC rail requirements. |
| DVS Resolution | 10mV steps from 0.5V to 1.45V for BUCK1 and BUCK2 - enables fine-grained CPU/GPU core voltage control during connected standby and performance states. |
| OTP Configuration | TPS650945 variant: LPDDR4 support, VTT disabled, BUCK6 = 1.1V default, Forced PWM on BUCK3–BUCK5 - eliminates auto-mode noise in memory subsystems. |
| I²C Interface | Standard (100kHz), Fast (400kHz), Fast Mode Plus (1MHz); fixed address 0x5E - enables real-time rail reconfiguration without interrupting SoC operation. |
| Thermal Protection | THOT = 115°C ±5°C (thermal shutdown), TCRIT = 145°C ±10°C (critical alert); RθJA = 25.8°C/W - requires thermal pad soldering to PCB ground plane for safe 21A operation. |
| Package | VQFN-64 (RSK), 8.0mm × 8.0mm, exposed thermal pad - optimized for high-density mobile PCB layouts with minimal footprint and efficient heat dissipation. |
Pinout & Package
VQFN-64 (RSK) package with 8.0mm × 8.0mm body and exposed thermal pad requiring connection to PCB ground plane via multiple vias for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| FBGND2 / FBVOUT2 | Remote sense pair for BUCK2 (VCCGI) | Enables accurate regulation at SoC die by compensating for PCB trace IR drop; must connect to VCCGI VSS/VCC SENSE points on host processor. |
| DRVH1 / DRVL1 / BOOT1 / SW1 | Gate drive and switch node for BUCK1 (VNN) | Drives external high-side/low-side FETs; BOOT1 requires 100nF ceramic capacitor to SW1 for bootstrap bias - defines maximum switching frequency and efficiency. |
| ILIM1 / ILIM2 / ILIM6 | Current limit programming pins | Set valley current limit for external low-side FETs using resistor-to-ground; ILIMREF = 50µA ±10% - determines OCP trip point and short-circuit robustness. |
| SLP_S0B / SLP_S3B / SLP_S4B | Power state control inputs | Hardware-triggered transitions into Connected Standby (S0iX), S3, and S4 states - bypasses I²C for deterministic, low-latency power sequencing. |
| PMICEN | Cold-boot enable | Rising edge initiates G3→S5/S4 transition; driven low shuts down all VRs - serves as primary system-level power-on reset signal. |
| DATA / CLK | I²C bidirectional interface | Address 0x5E; supports 1MHz Fast Mode Plus - used for DVS, rail enable/disable, fault register readback, and OTP configuration verification. |
Key Features
| Feature | Design Value |
|---|---|
| D-CAP2™ Buck Controllers | Enables fast transient response (<50mV undershoot) for BUCK1/BUCK2/BUCK6 without external compensation components - reduces BOM count and layout complexity. |
| Forced PWM Mode (BUCK3–BUCK5) | Eliminates frequency dithering and audible noise at light loads - essential for stable LPDDR4 memory timing and EMI compliance in ultrabooks. |
| VTT LDO Disable (OTP-configured) | Removes DDR termination rail when unused (e.g., LPDDR4-only designs), reducing quiescent current and simplifying power tree - improves battery life in always-on scenarios. |
| Integrated 3.3V/5V LDOs | LDO3P3 (3.3V/40mA) and LDO5P0 (5V/180mA) provide clean auxiliary rails for EC, sensors, and USB PHY - eliminates need for discrete LDOs in reference designs. |
| Load Switches with Slew Control | SWA1/SWB1/SWB2 support 0.5V–3.3V input, <96mΩ RDS(ON) at 1.8V, and programmable slew rate - prevents inrush current damage to downstream peripherals like displays and SSDs. |
Applications
| Intel Apollo Lake Tablet Power System | Ultrabook DDR3L Memory Subsystem |
|---|---|
Use Scenario: Compact tablet powered by 3S Li-ion battery (11.1V nominal) with Intel Apollo Lake SoC and LPDDR4 memory. IC Role / Device Role / Timing Role: Single-chip PMIC providing all core, I/O, and memory rails with hardware-based sequencing and I²C DVS for CPU/GPU voltage scaling. Use Value: Reduces solution size by 40% vs. discrete regulator approach; OTP-configured Forced PWM ensures noise-free LPDDR4 operation at 1.1V. |
Use Scenario: Fanless ultrabook using DDR3L memory with strict EMI limits and thermal constraints. IC Role / Device Role / Timing Role: Supplies VDDQ (1.35V), VTT (0.675V), and VCCIO (1.8V) with synchronized startup and precise remote sensing. Use Value: VTT disable option (TPS650945) removes unnecessary termination rail, cutting idle current by 120mA and extending battery runtime. |
| Wall-Powered Industrial PC | Mobile Internet Device with NVDC Architecture |
Use Scenario: DIN-rail mounted industrial PC powered from 12V DC supply, requiring high reliability and thermal resilience. IC Role / Device Role / Timing Role: Delivers 21A VCCGI rail with thermal foldback (TCRIT = 145°C) and robust overcurrent protection for long-term continuous operation. Use Value: RθJB = 4.4°C/W enables full-rated output without heatsink; 6.4mm² thermal pad area supports >2W dissipation under sustained load. |
Use Scenario: Portable medical data logger with non-NVDC architecture, dual input (battery + USB-C PD), and connected standby. IC Role / Device Role / Timing Role: Manages seamless transition between battery and adapter power while maintaining DDR self-refresh and RTC wake capability. Use Value: SLP_S0B-triggered Connected Standby mode draws only 65µA shutdown current - extends battery life to >14 days in sleep state. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS650944RSKT | OTP enables VTT, sets BUCK6 to 1.1V, uses Auto mode (not Forced PWM) for BUCK3–BUCK5 - higher light-load noise risk. | Required for DDR3L memory with active VTT termination; unsuitable for LPDDR4-only designs needing noise immunity. | Select only if VTT rail is mandatory and system-level EMI filtering can mitigate PWM auto-mode switching artifacts. |
| TPS650947RSKT | OTP enables VTT, sets BUCK6 to 1.35V, uses Forced PWM for BUCK3–BUCK5, and configures SWB1_2 via SLP_S3B - matches DDR3L timing. | Designed for DDR3L with 1.35V VDDQ and active VTT; supports deeper S3 entry than TPS650945. | Choose for DDR3L-based notebooks where VTT termination and 1.35V VDDQ are required, and SLP_S3B-driven load switch control is needed. |
Compared with TPS650944RSKT and TPS650947RSKT, the TPS650945A0RSKT uniquely combines LPDDR4 support, VTT disable, and Forced PWM on BUCK3–BUCK5 - making it the only variant optimized for noise-sensitive, VTT-free LPDDR4 memory subsystems in ultramobile platforms.
Availability
TPS650945A0RSKT is available at Aetrix Electronics and suitable for Intel Apollo Lake tablets, ultrabooks, and industrial PCs requiring stable component supply, long-lifecycle support, and guaranteed OTP configuration consistency across production batches.
Supply support for TPS650945A0RSKT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of collaboration on Intel platform reference designs.
The TPS65094 family was engineered specifically for Intel's Apollo Lake SoC power architecture - delivering tightly integrated, OTP-configurable, and thermally robust power solutions for next-generation mobile and IoT computing devices.
FAQ
What is the OTP configuration of TPS650945A0RSKT?
The TPS650945A0RSKT is factory-programmed with OTP settings for LPDDR4 memory support, VTT LDO disabled, BUCK6 default output of 1.1V, and Forced PWM mode enabled for BUCK3, BUCK4, and BUCK5. This configuration avoids light-load frequency switching noise and aligns with Intel Apollo Lake LPDDR4 reference designs. The DEVICEID register value is 0xDh, confirming this specific OTP variant.
Does TPS650945A0RSKT support DDR3L memory?
No, TPS650945A0RSKT does not support DDR3L memory because its OTP disables the VTT LDO and sets BUCK6 to 1.1V - incompatible with DDR3L's 1.35V VDDQ and mandatory VTT termination. For DDR3L, use TPS650947RSKT (1.35V VDDQ + enabled VTT) or TPS650944RSKT (1.1V VDDQ + enabled VTT). The TPS650945A0RSKT is strictly intended for LPDDR4-only platforms.
What is the purpose of Forced PWM mode on BUCK3–BUCK5 in TPS650945A0RSKT?
Forced PWM mode on BUCK3–BUCK5 in TPS650945A0RSKT eliminates auto-mode frequency dithering at light loads, preventing audible noise and EMI spikes that could disrupt LPDDR4 memory timing. This is explicitly recommended in TI documentation to avoid voltage undershoot/overshoot and potential shutdown events - a critical design requirement for stable LPDDR4 operation in ultrabooks and tablets.
How is thermal management implemented in TPS650945A0RSKT?
TPS650945A0RSKT incorporates dual thermal thresholds: THOT = 115°C triggers PROCHOT assertion to throttle the SoC, while TCRIT = 145°C initiates full thermal shutdown. Its RθJB = 4.4°C/W and exposed thermal pad require soldering to a multi-via PCB ground plane. Layout guidelines mandate ≥6 vias under the pad and minimum 200mm² copper area to sustain 21A BUCK2 operation without derating.
Can TPS650945A0RSKT be used with Intel Pentium N4200 processors?
Yes, TPS650945A0RSKT is fully compatible with Intel Pentium N4200 (Apollo Lake), as confirmed by TI's official platform support documentation and Intel's reference schematics. It satisfies all rail requirements - including VNN (BUCK1), VCCGI (BUCK2), VDDQ (BUCK6), VCCRAM (BUCK3), and V1P8A/V1P24A (BUCK4/BUCK5) - and implements the exact OTP configuration specified for Apollo Lake LPDDR4 designs.
TPS650945A0RSKT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 64-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- Controller/Converter, Mobile PCs
- Voltage - Input:
- 5.6V ~ 21V
- Number of Outputs:
- 12
- Voltage - Output:
- Multiple
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 64-VQFN (8x8)
TPS650945A0RSKT FAQ
1.How can I place an order for TPS650945A0RSKT through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS650945A0RSKT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS650945A0RSKT reliable?
The price and inventory of TPS650945A0RSKT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS650945A0RSKT is usually 5 days.
3.What payment methods are accepted for TPS650945A0RSKT?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS650945A0RSKT transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS650945A0RSKT?
TPS650945A0RSKT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS650945A0RSKT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS650945A0RSKT?
For technical support, including TPS650945A0RSKT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS650945A0RSKT requirements.
6.How does Aetrix verify that TPS650945A0RSKT is sourced from the original manufacturer or authorized distributors?
All TPS650945A0RSKT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS650945A0RSKT meets industry standards.
7.What is the process for return or replacement of TPS650945A0RSKT?
All TPS650945A0RSKT units undergo pre-shipment inspection (PSI). If there is an issue with TPS650945A0RSKT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS650945A0RSKT part is unused and in its original packaging.
Return procedure for TPS650945A0RSKT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TPS650945A0RSKT Tags
-
TPS51206DSQR
Texas Instruments
-
TPS51200DRCR
Texas Instruments
-
TPS51200DRCT
Texas Instruments
-
TPS62740DSSR
Texas Instruments
-
TPS51100DGQR
Texas Instruments
-
NCP51200MNTXG
onsemi
-
NCP51400MNTXG
onsemi
-
RT9026GSP
Richtek USA Inc.
-
LP2998MRX/NOPB
Texas Instruments
-
TPS51200QDRCRQ1
Texas Instruments
-
DPA423GN-TL
Power Integrations
-
LM10011SD/NOPB
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
