Texas Instruments TPS650947A0RSKT

Overview

TPS650947A0RSKT from Texas Instruments is a power-management IC (PMIC) designed for Intel™ Apollo Lake platforms, integrating six synchronous buck regulators (three controllers + three converters), three adjustable LDOs, one VTT LDO, and three slew-controlled load switches. It delivers 5A/7A/21A output capability across BUCK1/BUCK6/BUCK2, supports I²C dynamic voltage scaling (0.5V–1.45V in 10mV steps), and targets DDR3L memory termination with VTT IOCP ≥1.8A.

For engineers reviewing the TPS650947A0RSKT datasheet, TPS650947A0RSKT pinout, TPS650947A0RSKT application, or TPS650947A0RSKT equivalent, this page provides verified functional identity, OTP-specific configuration (DDR3L, VTT enabled, SLP_S3B-controlled SWB1_2, Forced PWM mode for BUCK3–BUCK5), thermal pad–based VQFN-64 package details, and validated alternative options aligned to Intel reference designs.

Technical Context

The TPS650947A0RSKT implements D-CAP2™ topology for high-efficiency, fast-transient BUCK1 (VNN), BUCK2 (VCCGI), and BUCK6 (VDDQ) controllers driving external FETs, while BUCK3 (VCCRAM), BUCK4 (V1P8A), and BUCK5 (V1P24A) use dcs-control topology with internal FETs and 3A/2A/2A rated outputs. All six VRs are sequenced and protected per Intel power-up requirements, including DDR3L-compatible VTT regulation and connected-standby support via SLP_S0B.

I²C interface (address 0x5E) enables full configuration of output voltages, DVS profiles, current limits (via ILIM1/ILIM2/ILIM6), and rail enable/disable states. OTP programming fixes BUCK6 default at 1.35V, enables VTT (IOCP min 1.8A), assigns SWB1_2 control to SLP_S3B, and forces PWM mode for BUCK3–BUCK5 to suppress light-load frequency switching noise.

Key Specifications

Pinout & Package

TPS650947A0RSKT uses an 8mm × 8mm, 64-pin VQFN package (RSK) with an exposed thermal pad that must be soldered to the system ground plane using multiple vias for optimal thermal and electrical performance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PMIC applications.

Compared with TPS650945A0RSKT and TPS650944A0RSKT, the TPS650947A0RSKT uniquely supports DDR3L memory via its enabled VTT LDO (1.8A IOCP) and fixed 1.35V BUCK6 default, making it the only option among the three for cost-optimized DDR3L-based Apollo Lake platforms requiring integrated termination.

Availability

TPS650947A0RSKT is available at Aetrix Electronics and suitable for Intel Apollo Lake tablets, DDR3L-based industrial PCs, and ultrabooks requiring stable component supply, long-term lifecycle support, and guaranteed OTP configuration integrity.

Supply support for TPS650947A0RSKT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of collaboration on Intel platform reference designs.

The TPS65094 family was developed specifically for Intel Apollo Lake processors, integrating all essential power rails, sequencing logic, and DDR memory support into a single VQFN package to minimize footprint and system cost in space-constrained mobile devices.

FAQ

What DDR memory standard does the TPS650947A0RSKT support?

The TPS650947A0RSKT is factory OTP-programmed for DDR3L support, including an enabled VTT LDO with minimum 1.8A IOCP and BUCK6 default output of 1.35V. It does not support LPDDR4 or DDR4; those require alternate OTP variants like TPS650945A0RSKT or TPS650944A0RSKT. The VTT regulation is fully compliant with JEDEC DDR3L termination specifications.

How is dynamic voltage scaling implemented on the TPS650947A0RSKT?

The TPS650947A0RSKT supports I²C-based dynamic voltage scaling (DVS) for BUCK1 (VNN) and BUCK2 (VCCGI) with 10mV resolution across 0.5V–1.45V. Voltage changes are executed via VID register writes (BUCK1_VID[6:0] and BUCK2_VID[6:0]) through the standard I²C interface (address 0x5E). Slew rate is fixed at 2.5–3.125 mV/µs to prevent overshoot during transitions.

What is the purpose of the Forced PWM mode on BUCK3–BUCK5 in the TPS650947A0RSKT?

Forced PWM mode on BUCK3 (VCCRAM), BUCK4 (V1P8A), and BUCK5 (V1P24A) is OTP-enabled in the TPS650947A0RSKT to eliminate abnormal frequency switching and minimize conducted noise at light loads. Without it, Auto mode can cause voltage undershoot/overshoot leading to system instability or shutdown - a known issue documented in TI's TPS65094 datasheet Section 4.1.

Which power state control pins manage load switches on the TPS650947A0RSKT?

On the TPS650947A0RSKT, SWB1 and SWB2 are controlled by the SLP_S3B pin (falling edge disables them), per OTP configuration. SWA1 is controlled by LDOLS_EN (active-high), which also enables LDOA2 and LDOA3. This differs from other variants like TPS650944A0RSKT, where Pin 14 functions as SWA1_EN only. All three switches feature slew-rate control to limit inrush current.

What thermal management features are built into the TPS650947A0RSKT?

The TPS650947A0RSKT includes dual thermal thresholds: THOT (110–120°C) triggers PROCHOT assertion to throttle the SoC, and TCRIT (130–160°C) initiates full shutdown. It also features a low R_θJB of 4.4°C/W due to its exposed thermal pad, enabling reliable operation up to +85°C ambient. Thermal sensors feed IRQB for fault reporting and support closed-loop thermal management in conjunction with the host EC.