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Texas Instruments TPS65100PWP
- Part No.:
- TPS65100PWP
- Manufacturer:
- Texas Instruments
- Category:
- Special Purpose Regulators
- Package:
- 24-PowerTSSOP (0.173", 4.40mm Width)
- Datasheet:
-
TPS65100PWP.pdf
- Description:
- IC REG CTRLR TFT 4OUT 24HTSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:919
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Product details
Overview
TPS65100PWP from Texas Instruments is a triple-output LCD power supply IC integrating a 1.6-MHz boost converter (VO1 up to 15 V / 350 mA), dual regulated charge pumps (VO2 down to –12 V / 20 mA; VO3 up to 30 V / 20 mA), an integrated VCOM buffer, and a 3.3-V linear regulator controller - all in a single HTSSOP-24 package for TFT LCD panel biasing.
For engineers reviewing the TPS65100PWP datasheet, TPS65100PWP pinout, TPS65100PWP application, or TPS65100PWP equivalent, this device delivers precise, sequenced, fault-protected voltage rails for notebook and industrial display systems requiring compact, high-frequency, multi-rail DC/DC conversion with integrated VCOM buffering and external LDO control.
Technical Context
The TPS65100PWP implements a fixed-frequency (1.6 MHz) PWM boost converter with virtual synchronous operation using an internal P-MOSFET (rDS(on) ≈ 15 Ω) and external Schottky diode, enabling continuous conduction mode across full load range. Its feedback regulation uses 1.146-V reference at FB1, with ±1% VO1 accuracy over line/load/temperature.
It integrates three independent regulated outputs: a negative charge pump (VO2) with FB2-based regulation referenced to GND, a positive charge pump (VO3) with FB3 and tripler/doubler mode selection via C2-/MODE pin, and a VCOM buffer with soft-start and VCOMIN-controlled enable - all powered from the SUP rail tied to VO1.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.7 V to 5.8 V - supports direct connection to single-cell Li-ion or 3.3/5-V system rails without pre-regulation. |
| VO1 Boost Output | Up to 15 V / 350 mA - main source drive voltage for TFT LCD gate drivers; <1% output voltage accuracy ensures stable pixel charging. |
| VO2 Negative Pump | Down to –12 V / 20 mA - regulated negative gate bias; uses external Schottky diodes and FB2 feedback for precision inversion of VO1. |
| VO3 Positive Pump | Up to 30 V / 20 mA - configurable as doubler or tripler via C2-/MODE pin; enables flexible gate-on voltage scaling for varying panel designs. |
| VCOM Buffer Output | Driven from VCOMIN input; supports soft-started backplane bias up to VO1–2 V; quiescent current ≤1.3 mA when active. |
| Linear Regulator Control | 3.3-V fixed output via external NPN/PNP transistor (BASE pin); FB4 sets regulation point; ENR enables independent sequencing. |
| Fault Protection | Full output fault detection (VO1/VO2/VO3) with automatic shutdown - TPS65100PWP enters latch-off on any rail undervoltage/overvoltage event. |
Pinout & Package
TPS65100PWP is housed in a 24-pin HTSSOP (PWP) package measuring 7.80 mm × 4.40 mm with exposed PowerPAD™ thermal die connected to PGND pins.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN (Pin 4) | Main input supply | Accepts 2.7–5.8 V; powers internal logic and gate drivers; connects to system battery or DC rail. |
| SW (Pins 5,6) | Boost switch node | Drives external inductor; requires low-ESR ceramic capacitor and Schottky diode to SUP for energy transfer. |
| SUP (Pin 9) | Supply rail for charge pumps & VCOM | Must be connected directly to VO1 output; supplies bias for VO2/VO3 regulators and VCOM buffer - no bypass cap recommended. |
| FB1 (Pin 1) | VO1 feedback input | Connects to resistive divider from VO1; regulates at 1.146 V reference; enables precise VO1 setting (e.g., 10 V, 12 V, 15 V). |
| FB2 (Pin 21) | VO2 feedback input | Monitors negative output; enables accurate –5 V to –12 V regulation with external resistor network tied to GND. |
| FB3 (Pin 12) | VO3 feedback input | Configures positive pump output; supports 2× or 3× multiplication of VO1 depending on C2-/MODE pin state. |
| C2-/MODE (Pin 15) | Charge pump mode select | Ground = doubler mode; connected to flying cap = tripler mode; determines VO3 output ratio relative to VO1. |
| VCOMIN (Pin 11) | VCOM buffer input | When >1.0 V, enables VCOM output; tie to GND to disable buffer and reduce quiescent current. |
| EN (Pin 24) | Main enable input | Active-high logic control; initiates full power-on sequence: VO1 → VO2 → VO3 → VCOM; must be terminated. |
| ENR (Pin 23) | LDO controller enable | Independent enable for 3.3-V linear regulator; allows asynchronous startup or shutdown of logic rail. |
| BASE (Pin 3) | External transistor base drive | Drives NPN/PNP pass transistor for 3.3-V LDO; current-limited to 27 mA max; ties to VIN if regulator unused. |
| REF (Pin 20) | Internal reference output | Stable 1.213-V reference; usable for external monitoring or calibration circuits; buffered and low-noise. |
Key Features
| Feature | Design Value |
|---|---|
| Virtual Synchronous Converter | Enables continuous conduction mode at light loads using internal P-MOSFET + external Schottky, eliminating switching ripple and simplifying compensation. |
| Integrated Power-On Sequencing | Hardware-controlled startup order (VO1 → VO2 → VO3 → VCOM) with per-rail soft-start prevents inrush-induced input droop and panel flicker. |
| Fault Detection & Shutdown | Monitors all four outputs (VO1/VO2/VO3/VCOM); latches off on first fault - critical for display reliability in automotive/industrial environments. |
| VCOM Buffer with Soft-Start | Eliminates large transient currents during panel initialization; VCOMIN threshold ensures buffer only activates after stable VO3 is established. |
| Tripler/Doubler Mode Flexibility | C2-/MODE pin selects charge pump topology - supports diverse LCD panel requirements (e.g., 18 V for 6.5″, 27 V for 10.1″) without redesign. |
Applications
| TFT Notebook Display | Industrial HMI Panel |
|---|---|
|
Use Scenario: Powering 13.3″–15.6″ active-matrix TFT panels in portable computing devices with single 3.3/5-V or Li-ion input. IC Role / Device Role / Timing Role: Generates synchronized VO1 (12 V), VO2 (–7 V), VO3 (24 V), and VCOM (6 V) with sub-100-ms sequencing for glitch-free boot. Use Value: Replaces 4 discrete DC/DC converters and 1 op-amp buffer; reduces BOM count by ≥7 components and PCB area by >40%. |
Use Scenario: Driving ruggedized 7″–12″ sunlight-readable displays in factory automation HMIs operating from 24-V DC with local 5-V conversion. IC Role / Device Role / Timing Role: Delivers fault-protected, thermally robust bias rails under wide temperature (–40°C to +85°C) and variable load conditions. Use Value: Built-in thermal shutdown and output fault latching prevent field failures; HTSSOP package supports standard reflow and manual repair. |
| Automotive Infotainment | Medical Diagnostic Monitor |
|
Use Scenario: Supplying LCD backlight and gate drivers in car navigation systems with ISO 16750-compliant 9–16-V input (via external 5-V pre-regulator). IC Role / Device Role / Timing Role: Provides ESD-hardened (±2 kV HBM), AEC-Q200-aligned power rails with controlled startup to meet automotive EMC and safety requirements. Use Value: Eliminates need for external watchdog or sequencing IC; integrated fault reporting simplifies diagnostic software integration. |
Use Scenario: Biasing high-resolution monochrome TFT panels in portable ultrasound and patient monitors where display stability is life-critical. IC Role / Device Role / Timing Role: Delivers ultra-stable VO1 (<0.2%/A load regulation) and VCOM (≤37 mV DC load shift at ±100 mA) for consistent grayscale fidelity. Use Value: Internal soft-start and rail-specific fault isolation prevent display corruption during power transients or component aging. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LCD bias supply applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65105PWP | Lower switch current limit (1.37 A vs. 2.3 A); optimized for lower-power panels (≤10″) with smaller inductors. | Reduced VO1 output capability (≤250 mA typical); unsuitable for high-resolution 15.6″+ panels requiring >300 mA source drive. | Select when panel power demand is ≤200 mA and board space constraints favor smaller magnetics. |
| MAX1664ETJ+ | 3-output architecture (no VCOM buffer or LDO controller); uses different charge pump topology; 1.2-MHz switching frequency. | Lacks integrated VCOM buffering and linear regulator control - requires two additional ICs for full TFT bias solution. | Choose only if existing design already implements discrete VCOM/LDO and cost-per-rail is prioritized over integration. |
Compared with TPS65100PWP, TPS65105PWP offers reduced power delivery but improved efficiency at light loads, while MAX1664ETJ+ provides basic triple-rail generation without VCOM or LDO integration - making TPS65100PWP the only single-chip solution supporting full TFT panel biasing with fault protection and sequencing.
Availability
TPS65100PWP is available at Aetrix Electronics and suitable for TFT LCD displays for notebooks, industrial HMIs, and automotive infotainment systems requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for TPS65100PWP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies with over 50 years of innovation in high-reliability power solutions.
The TPS6510x product line was designed specifically for compact, high-frequency TFT LCD biasing in space-constrained portable and industrial displays - integrating boost, dual charge pumps, VCOM buffering, and LDO control into one IC to eliminate discrete power subsystems.
FAQ
What is the maximum output current capability of the TPS65100PWP's main boost converter (VO1)?
The TPS65100PWP's main boost converter delivers up to 350 mA at VO1, supported by a 2.3-A typical switch current limit and optimized for stable operation with 4.7-µH inductors. This rating holds across the full input range (2.7–5.8 V) and operating temperature (–40°C to +85°C), with load regulation specified at 0.2%/A. The TPS65100PWP maintains this performance using virtual synchronous operation to sustain continuous conduction mode even at light loads.
Does the TPS65100PWP include built-in fault protection, and how does it respond to an output fault?
Yes, the TPS65100PWP includes comprehensive fault protection for all four regulated outputs (VO1, VO2, VO3, and VCOM). When any output falls outside its programmed regulation window - such as VO1 dropping below 91.25% of setpoint or VO2 exceeding –13% of nominal - the TPS65100PWP immediately enters latch-off shutdown. Recovery requires toggling the EN pin low then high. This behavior distinguishes the TPS65100PWP from the TPS65101, which lacks this feature.
How is the positive charge pump (VO3) configured for voltage tripling versus doubling on the TPS65100PWP?
The TPS65100PWP's positive charge pump operates in voltage tripler mode when the flying capacitor is connected between C1+ and C2-/MODE pins; it switches to doubler mode when C2-/MODE is grounded and the flying capacitor is omitted. This configuration is hardware-selectable and does not require firmware or external logic. The TPS65100PWP datasheet specifies VO3 output ranges of up to 27 V (tripler) or 18 V (doubler) depending on VO1 and load, with 20-mA minimum output current guaranteed in both modes.
Can the VCOM buffer in the TPS65100PWP be disabled, and what is the impact on quiescent current?
Yes, the VCOM buffer in the TPS65100PWP can be fully disabled by connecting VCOMIN (Pin 11) to GND. This action halts VCOM output and reduces total quiescent current by approximately 0.75 mA - from ~1.3 mA (active) to ~0.55 mA (disabled) - as confirmed in the electrical characteristics table. The TPS65100PWP's VCOMIN threshold is ~1.0 V, so dynamic grounding during operation is not permitted; static GND tie is required for reliable disable.
What package type and thermal characteristics apply to the TPS65100PWP?
The TPS65100PWP is exclusively offered in the 24-pin HTSSOP (PWP) package with PowerPAD™ thermal pad, measuring 7.80 mm × 4.40 mm. Its junction-to-ambient thermal resistance (RθJA) is 37.2°C/W under standard JEDEC PCB conditions, and the exposed thermal die must be soldered to a PGND copper plane for optimal heat dissipation. The TPS65100PWP supports continuous operation up to +125°C junction temperature, with thermal shutdown activating at +160°C.
TPS65100PWP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 24-PowerTSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Applications:
- Controller, TFT LCD
- Voltage - Input:
- 2.7V ~ 5.8V
- Number of Outputs:
- 4
- Voltage - Output:
- Multiple
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-HTSSOP
TPS65100PWP FAQ
1.How can I place an order for TPS65100PWP through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS65100PWP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS65100PWP reliable?
The price and inventory of TPS65100PWP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS65100PWP is usually 5 days.
3.What payment methods are accepted for TPS65100PWP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS65100PWP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS65100PWP?
TPS65100PWP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS65100PWP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS65100PWP?
For technical support, including TPS65100PWP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS65100PWP requirements.
6.How does Aetrix verify that TPS65100PWP is sourced from the original manufacturer or authorized distributors?
All TPS65100PWP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS65100PWP meets industry standards.
7.What is the process for return or replacement of TPS65100PWP?
All TPS65100PWP units undergo pre-shipment inspection (PSI). If there is an issue with TPS65100PWP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS65100PWP part is unused and in its original packaging.
Return procedure for TPS65100PWP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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