Texas Instruments TPS65110RGER
- Part No.:
- TPS65110RGER
- Manufacturer:
- Texas Instruments
- Category:
- Special Purpose Regulators
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
TPS65110RGER.pdf
- Description:
- IC REG CHRG PUMP LTPS 3OUT 24QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
TPS65110RGER from Texas Instruments is a triple-output charge pump IC designed for LTPS-LCD bias generation, delivering fixed 3.3 V (16 mA), 7.5 V (2 mA), and −2.7 V (1 mA) outputs from a 2.4–5.5 V input. It features autonomous VCC boost ratio selection (x1.0/x1.33/x1.5/x2.0), 5 mV typical VCC ripple at 5 mA, and integrated sequential power-up/down control. It targets compact handheld LCD displays requiring precise, low-noise analog and dual-polarity supply rails.
For engineers reviewing the TPS65110RGER datasheet, TPS65110RGER pinout, TPS65110RGER application, or TPS65110RGER equivalent, key selection considerations include its fixed-output LTPS-LCD bias architecture, 24-pin QFN package with flying capacitor interface, ultra-low ripple performance on VCC, and compatibility with small-form-factor portable display power designs.
Technical Context
The TPS65110RGER implements three independent regulated charge pump stages: VCC uses an autonomous boost-ratio controller (x1.0 to x2.0) with SKIP-mode operation and 400 kHz max switching frequency; VDD is a fixed-ratio (x3) positive boost stage powered by VCC; VSS is a fixed-ratio (x−1) inverting stage also powered by VCC. All outputs are internally sequenced during power-up (VCC → VSS → VDD) and power-down (VDD → VSS → VCC).
It integrates I²C-compatible serial control (CLK/DATA), enable logic (EN), EEPROM power (VROM), and dedicated flying capacitor terminals for each output stage - CCP1/CCN1 through CCP3/CCN3 for VCC, CDP1/CDN1 through CDP3/CDN3 for VDD, and CSP1/CSN1 for VSS - with separate analog (AGND) and power (PGND) ground returns.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input voltage range | 2.4 V to 5.5 V - supports single-cell Li-ion or Li-poly battery input without external regulation |
| VCC output | 3.3 V ±1.5%, 16 mA - primary analog rail for LCD source drivers; 5 mV ripple enables stable gate biasing |
| VDD output | 7.5 V ±3%, 2 mA - fixed x3 boost from VCC; powers LCD gate drivers requiring higher positive voltage |
| VSS output | −2.7 V ±3%, 1 mA - fixed inverting output; supplies negative common electrode or gate bias |
| Quiescent current | 50 µA typical - minimizes standby power in always-on display subsystems |
| Shutdown current | <1 µA - enables deep-sleep mode for extended battery life in portable devices |
| Package | 24-pin QFN (4 mm × 4 mm, RGE) - thermally enhanced for high-density portable PCB layouts |
Pinout & Package
TPS65110RGER is housed in a 24-pin VQFN package (RGE drawing) with exposed thermal pad. Pin 1 is CSP1 (VSS flying cap positive terminal); pins 2–8 serve VCC and its flying capacitors; pins 9–12 handle input, control, and enable; pins 13–14 are AGND/VROM; pins 15–21 manage VDD and its flying caps; pins 22–24 are PGND, VSS, and CSN1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CSP1 | VSS flying capacitor positive terminal | Connects to positive side of external 0.1 µF capacitor for VSS charge pump operation |
| VCC | Main analog supply output | Delivers regulated 3.3 V to LCD analog circuitry; requires 2.2 µF output capacitor |
| CCP1–CCP3 / CCN1–CCN3 | VCC flying capacitor terminals | Three differential pairs for 0.22 µF flying caps enabling high-current, low-ripple VCC generation |
| VIN | Main input supply | Accepts 2.4–5.5 V; requires 4.7 µF input capacitor for stability under transient load |
| EN | Enable logic input | Active-high signal initiating internal power sequencing; must not float |
| CLK / DATA | I²C serial interface inputs | Support configuration and status monitoring; compatible with standard 100 kHz I²C timing |
| VROM | EEPROM power supply | Provides regulated power to internal nonvolatile memory storing device settings |
| VDD | Positive gate driver supply | Fixed 7.5 V output; powers row drivers requiring higher voltage than VCC |
| CDP1–CDP3 / CDN1–CDN3 | VDD flying capacitor terminals | Three differential pairs for 0.1 µF flying caps supporting x3 boost topology |
| VSS | Negative supply output | Regulated −2.7 V rail; requires 2.2 µF output capacitor and 0.1 µF flying cap |
| CSN1 | VSS flying capacitor negative terminal | Completes VSS charge pump loop with CSP1; critical for inverting efficiency |
| AGND / PGND | Analog and power ground returns | Separate ground paths minimize noise coupling between sensitive analog and switching sections |
Key Features
| Feature | Design Value |
|---|---|
| Autonomous VCC boost ratio selection | Automatically selects x1.0/x1.33/x1.5/x2.0 based on VIN–VCC delta, optimizing efficiency across battery discharge |
| Integrated sequential power control | Hardwired VCC→VSS→VDD power-up and VDD→VSS→VCC power-down order prevents LCD latch-up or image artifacts |
| Ultra-low VCC output ripple | 5 mV typical at 5 mA load enables clean analog biasing for high-resolution LTPS panels without additional LDO post-regulation |
| Dedicated flying capacitor interface | 12 dedicated pins (CCP/CCN/CDP/CDN/CSP/CSN) simplify layout and reduce EMI vs. shared-capacitor topologies |
| Sub-1 µA shutdown current | Enables true zero-power display sleep states in PDAs and smartphones, extending battery runtime |
Applications
| LTPS-LCD Panel Biasing | Smartphone Display Power |
|---|---|
Use Scenario: Driving high-resolution low-temperature polysilicon (LTPS) LCD panels in handheld devices where tight voltage tolerance and low noise are mandatory. IC Role / Device Role / Timing Role: Triple-output bias generator providing simultaneous 3.3 V analog, 7.5 V gate-on, and −2.7 V common electrode voltages with controlled sequencing. Use Value: Eliminates need for three discrete DC/DC converters; 5 mV VCC ripple ensures stable grayscale rendering and eliminates visible banding. | Use Scenario: Compact display sub-system in space-constrained smartphones requiring minimal BOM count and PCB area. IC Role / Device Role / Timing Role: Single-chip LTPS-LCD power manager integrating input UVLO, enable-controlled sequencing, and I²C-configurable operation. Use Value: Reduces solution size by >40% vs. discrete charge pumps; 24-pin QFN fits within narrow bezel margins. |
| PDA Main Display Supply | Pocket PC System Power |
Use Scenario: Primary display power in legacy PDAs operating from aging Li-ion batteries with wide voltage sag (2.8–4.2 V). IC Role / Device Role / Timing Role: Adaptive charge pump regulator maintaining 3.3 V VCC output despite input droop, using autonomous x1.33→x1.5 boost transition. Use Value: Extends usable battery life by sustaining display functionality down to 2.4 V input without brownout resets. | Use Scenario: Integrated power solution for Pocket PCs needing coordinated startup of display, backlight, and processor rails. IC Role / Device Role / Timing Role: Sequencing controller ensuring VCC stabilizes before enabling VSS/VDD, preventing panel damage during cold start. Use Value: Guarantees robust first-power reliability across temperature (−40°C to 85°C) and voltage extremes. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LTPS-LCD bias applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65111RGER | Fixed 5.0 V / 9.0 V / −3.0 V outputs; x2 VDD boost; higher VCC efficiency (90% at 10 mA) | Targets newer LTPS panels requiring higher gate-on voltage; less suitable for legacy 3.3 V/7.5 V designs | Select when panel specs demand 5 V VCC and 9 V VDD; verify VSS load capability matches −3.0 V requirement |
| MAX1627EAP+ | Triple-output, but uses inductor-based topology; 3.3 V/15 V/−15 V outputs; no integrated sequencing | Suitable for industrial LCDs needing higher voltage swing; requires external sequencing logic and magnetics | Choose only if design tolerates larger footprint and higher EMI; not drop-in due to different topology and pinout |
Compared with TPS65111RGER, the TPS65110RGER provides lower VCC/VDD voltages optimized for older LTPS panels and tighter VCC ripple spec, while MAX1627EAP+ offers higher output voltages at the cost of board area and complexity - making TPS65110RGER the preferred choice for compact, low-noise 3.3 V–based display systems.
Availability
TPS65110RGER is available at Aetrix Electronics and suitable for LTPS-LCD biasing, portable display power management, and handheld device analog supply applications requiring stable component supply and long-term design continuity.
Supply support for TPS65110RGER includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and power management technologies, with leadership in precision power solutions for portable electronics.
The TPS65110RGER belongs to TI's LCD bias power management product line, engineered specifically for low-noise, triple-rail generation in space-constrained LTPS-LCD applications such as smartphones and PDAs.
FAQ
What is the primary function of the TPS65110RGER in an LTPS-LCD system?
The TPS65110RGER serves as a complete triple-output bias power supply for LTPS-LCD panels, generating precisely regulated 3.3 V (VCC), 7.5 V (VDD), and −2.7 V (VSS) rails from a single 2.4–5.5 V input. Its integrated charge pump architecture, autonomous VCC boost control, and hardwired power sequencing eliminate external components and ensure reliable panel startup/shutdown - making it central to display subsystem power integrity in compact handheld devices.
Does the TPS65110RGER support I²C communication, and what is its role?
Yes, the TPS65110RGER supports I²C communication via CLK and DATA pins, enabling readback of status registers and configuration of certain internal parameters. While the core outputs are fixed, this interface allows system-level monitoring of fault conditions, power-good status, and thermal warnings - enhancing system diagnostics without requiring additional supervisory ICs in the TPS65110RGER-based design.
How does the TPS65110RGER achieve ultra-low 5 mV VCC output ripple?
The TPS65110RGER achieves 5 mV typical VCC ripple through a combination of autonomous multi-ratio charge pump operation, optimized flying capacitor sizing (three 0.22 µF caps), SKIP-mode control at light loads, and dedicated low-ESR output capacitance (2.2 µF). This architecture minimizes switching noise injection into the analog rail - a critical requirement for high-fidelity grayscale reproduction in LTPS-LCDs - and is validated across temperature and load conditions per the SLVS495 datasheet.
What are the key differences between TPS65110RGER and TPS65111RGER?
The TPS65110RGER delivers 3.3 V/7.5 V/−2.7 V outputs with x3 VDD boost, while the TPS65111RGER provides 5.0 V/9.0 V/−3.0 V with x2 VDD boost. The TPS65110RGER exhibits slightly lower VCC efficiency (86% vs. 90% at 10 mA) but superior VSS efficiency (82% vs. 58%) due to its −2.7 V output. Both share identical pinout, package, and sequencing logic - making them functionally similar but electrically distinct for specific panel voltage requirements.
Is the TPS65110RGER suitable for new designs, and what is its lifecycle status?
No - the TPS65110RGER is marked "Not Recommended for New Designs" and classified as OBSOLETE by Texas Instruments per the PACKAGE OPTION ADDENDUM. While still available through authorized distributors and Aetrix Electronics for legacy system support and repair, TI recommends evaluating newer alternatives like the TPS65132 or TPS65136 for new projects requiring extended longevity, improved efficiency, or enhanced feature sets.
TPS65110RGER Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Applications:
- Charge Pump, LTPS LCD
- Voltage - Input:
- 2.4V ~ 5.5V
- Number of Outputs:
- 3
- Voltage - Output:
- -2.7V, 3.3V, 7.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-VQFN (4x4)
TPS65110RGER FAQ
1.How can I place an order for TPS65110RGER through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS65110RGER on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS65110RGER reliable?
The price and inventory of TPS65110RGER are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS65110RGER is usually 5 days.
3.What payment methods are accepted for TPS65110RGER?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS65110RGER transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS65110RGER?
TPS65110RGER orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS65110RGER order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS65110RGER?
For technical support, including TPS65110RGER datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS65110RGER requirements.
6.How does Aetrix verify that TPS65110RGER is sourced from the original manufacturer or authorized distributors?
All TPS65110RGER products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS65110RGER meets industry standards.
7.What is the process for return or replacement of TPS65110RGER?
All TPS65110RGER units undergo pre-shipment inspection (PSI). If there is an issue with TPS65110RGER, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS65110RGER part is unused and in its original packaging.
Return procedure for TPS65110RGER:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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