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Texas Instruments TPS65110RGERG4
- Part No.:
- TPS65110RGERG4
- Manufacturer:
- Texas Instruments
- Category:
- Special Purpose Regulators
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
TPS65110RGERG4.pdf
- Description:
- IC REG CHRG PUMP LTPS 3OUT 24QFN
- Quantity:
- Payment:
- Shipping:
Inventory:3,014
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Product details
Overview
TPS65110RGERG4 from Texas Instruments is a triple-output charge pump IC designed for LTPS-LCD bias generation, delivering fixed 3.3 V (16 mA), 7.5 V (2 mA), and −2.7 V (1 mA) outputs from a 2.4–5.5 V input. It features autonomous VCC boost selection (x1.0/x1.33/x1.5/x2.0), 5 mV typical VCC ripple at 5 mA, and sequential power-up/down control - deployed in compact handheld LCD displays.
For engineers reviewing the TPS65110RGERG4 datasheet, TPS65110RGERG4 pinout, TPS65110RGERG4 application, or TPS65110RGERG4 equivalent, key selection criteria include guaranteed 16-mA VCC output with <1.5% accuracy, ultra-low-ripple performance critical for analog LCD supply, integrated sequencing for display power integrity, and QFN-24 package compatibility with space-constrained portable designs.
Technical Context
The TPS65110RGERG4 implements three independent regulated charge pump stages: VCC uses adaptive boost ratio selection and SKIP-mode operation to maintain efficiency across input voltage and load variations; VDD and VSS are fixed-ratio (x3 and x−1) pumps powered from VCC, enabling coordinated bias generation without external control logic. All outputs feature internal regulation and thermal-safe current limiting.
Power sequencing is fully autonomous: VCC rises first, followed by VSS at 75% of nominal, then VDD; shutdown follows reverse order (VDD → VSS → VCC) even during abrupt VIN drop. The device integrates I²C-compatible serial interface pins (CLK/DATA), EEPROM power (VROM), and enable-controlled shutdown drawing <1 µA.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Output | 3.3 V ±1.5%, delivers 16 mA - sufficient to drive LTPS panel analog supply and power downstream VDD/VSS pumps. |
| VDD Output | 7.5 V ±3%, delivers 2 mA - fixed x3 boost from VCC, used for LCD gate driver positive bias. |
| VSS Output | −2.7 V ±3%, delivers 1 mA - fixed inverting (x−1) charge pump for LCD common electrode negative bias. |
| Input Range | 2.4 V to 5.5 V - supports single-cell Li-ion, Li-poly, or dual-cell alkaline inputs without external regulators. |
| Quiescent Current | 50 µA typical - enables low-power standby in battery-operated PDAs and smartphones. |
| VCC Ripple | 5 mV typical at 5 mA - meets stringent analog supply noise requirements for high-resolution LTPS-LCD image fidelity. |
| Shutdown Current | <1 µA - minimizes battery drain during display off-state in portable devices. |
| Package | 24-pin VQFN (RGE), 4 mm × 4 mm - surface-mount footprint optimized for thin, space-constrained handheld PCBs. |
Pinout & Package
TPS65110RGERG4 is housed in a thermally enhanced 24-pin VQFN (RGE) package with exposed thermal pad (Pin 25). Pin functions are validated per TI SLVS495 datasheet Figure 5 (Top View) and Terminal Functions table.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN (Pin 9) | Main power input | Accepts 2.4–5.5 V; powers VCC pump and internal circuitry - requires 4.7 µF ceramic input capacitor. |
| VCC (Pin 2) | Primary regulated output | 3.3 V bias rail; supplies analog section of LTPS-LCD and feeds VDD/VSS charge pumps - needs 2.2 µF output cap. |
| VDD (Pin 15) | Positive auxiliary output | 7.5 V gate driver supply; generated from VCC via fixed x3 boost - requires 1.0 µF output capacitor. |
| VSS (Pin 23) | Negative auxiliary output | −2.7 V common electrode bias; generated from VCC via fixed inverting charge pump - needs 2.2 µF output cap. |
| EN (Pin 12) | Enable control input | Active-high logic; initiates full power sequence when pulled high - must not float to prevent erratic startup. |
| CLK/DATA (Pins 11/10) | I²C serial interface | Supports configuration and status readback; operates at up to 400 kHz - requires pull-up resistors to VCC. |
| AGND/PGND (Pins 13/22) | Analog & power ground | Separate GND pins minimize noise coupling between sensitive analog regulation and high-current switching paths. |
| CCP1–CCP3 / CCN1–CCN3 (Pins 8,6,4 / 7,5,3) | VCC flying capacitor terminals | Three 0.22 µF flying caps enable 16 mA VCC output; layout symmetry critical for ripple suppression. |
| CDP1–CDP3 / CDN1–CDN3 (Pins 21,16,17 / 20,18,19) | VDD flying capacitor terminals | Three 0.1 µF flying caps support x3 boost; placement near pins reduces ESR-induced losses. |
| CSN1/CSP1 (Pins 24/1) | VSS flying capacitor terminals | Two 0.1 µF flying caps implement inverting topology - CSP1 connects to VSS output, CSN1 to PGND. |
Key Features
| Feature | Design Value |
|---|---|
| Autonomous VCC boost ratio selection | Switches among x1.0/x1.33/x1.5/x2.0 based on VIN–VCC delta - maintains >84% efficiency across battery discharge curve. |
| Integrated sequential power control | Guarantees VCC→VSS→VDD power-up and VDD→VSS→VCC power-down - prevents LCD panel latch-up or image retention. |
| Ultra-low VCC output ripple | 5 mV typical at 5 mA - eliminates visible noise bands on high-contrast LTPS-LCD screens without additional LC filtering. |
| Sub-µA shutdown mode | <1 µA supply current - extends battery life in always-on portable devices during display sleep cycles. |
| Dedicated VROM supply | Separate 2.4–5.5 V input for internal EEPROM - isolates memory power from noisy switching rails to ensure reliable configuration storage. |
| Thermal and UVLO protection | Under-voltage lockout activates below 2.2 V (rising), and junction temperature limited to 125°C - prevents malfunction under brownout or overload. |
Applications
| LTPS-LCD Panel Bias Supply | Smartphone Display Power Management |
|---|---|
|
Use Scenario: Powering low-temperature polysilicon (LTPS) LCD panels in sub-100 g handheld devices with tight board area constraints. IC Role / Device Role / Timing Role: Single-chip triple-bias generator providing VCC (analog core), VDD (gate driver positive), and VSS (common electrode negative) with synchronized startup/shutdown. Use Value: Eliminates need for three discrete DC/DC converters and external sequencing logic - reduces BOM count by ≥7 components and saves >15 mm² PCB area. |
Use Scenario: Enabling rapid display wake/sleep transitions in battery-powered smartphones requiring <1 µA off-state current. IC Role / Device Role / Timing Role: System-level power controller that coordinates LCD bias rail sequencing with AP-side EN signal to avoid visual artifacts during screen on/off. Use Value: Achieves consistent 50-ms power-up time and eliminates ghosting/flicker during UI transitions - verified across −40°C to 85°C operating range. |
| PDA Main Display Power | Pocket PC Analog Front-End Supply |
|
Use Scenario: Delivering stable bias to high-resolution VGA LTPS-LCDs in legacy PDAs with single-cell Li-ion batteries (3.0–4.2 V). IC Role / Device Role / Timing Role: Input-voltage-adaptive charge pump maintaining 3.3 V VCC within ±1.5% despite battery sag - directly powering column driver ICs. Use Value: Sustains display contrast and grayscale linearity over full battery discharge cycle - no external feedback compensation required. |
Use Scenario: Providing clean, low-noise analog supply for touch controller and digitizer front-end in clamshell-form-factor Pocket PCs. IC Role / Device Role / Timing Role: Low-ripple VCC output (5 mV typ.) acting as reference-grade analog rail - decoupled from digital switching noise via AGND/PGND separation. Use Value: Reduces touch sensing error rate by >40% compared to switched-capacitor solutions without dedicated analog ground routing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LCD bias generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65111RGER | Delivers 5.0 V / 9.0 V / −3.0 V outputs; higher VCC voltage enables wider input compatibility but reduces margin for 3.3-V-only panels. | Targeted at newer LTPS panels requiring higher gate drive voltage; not drop-in for 3.3-V VCC systems without regulator redesign. | Select only if panel datasheet specifies 5.0 V VCC and 9.0 V VDD - verify VCC load capability remains ≥16 mA under new conditions. |
| MAX1672EUB+ | Single-output 3.3 V charge pump (150 mA); lacks integrated VDD/VSS generation and sequencing - requires two additional ICs for full bias solution. | Suitable for simpler STN/TFT panels without negative bias; cannot replace TPS65110RGERG4 in LTPS systems needing triple-rail coordination. | Consider only for cost-sensitive non-LTPS displays where external sequencing and discrete negative supply are acceptable. |
Compared with TPS65111RGER, TPS65110RGERG4 provides tighter VCC accuracy (±1.5% vs ±2%) and lower VCC ripple (5 mV vs 5 mV typical but higher max), while MAX1672EUB+ requires complete redesign to achieve equivalent functionality - making TPS65110RGERG4 the optimal choice for legacy LTPS-LCD bias where 3.3 V/7.5 V/−2.7 V rails are specified.
Availability
TPS65110RGERG4 is available at Aetrix Electronics and suitable for small-form LTPS-LCD displays, PDAs, and smartphone display subsystems requiring stable component supply and long-term obsolescence mitigation support.
Supply support for TPS65110RGERG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with over 50 years of innovation in high-reliability power conversion ICs.
The TPS65110RGERG4 belongs to TI's LCD bias power management product line, engineered specifically to consolidate multi-rail display power into a single QFN package for portable consumer electronics with stringent size and efficiency demands.
FAQ
What is the recommended input capacitor value for TPS65110RGERG4?
The TPS65110RGERG4 requires a minimum 4.7 µF ceramic input capacitor (Ci) placed close to VIN and PGND pins to stabilize the input rail and suppress switching noise. TI specifies X5R or X7R dielectric with ≤100 mΩ ESR; larger values (e.g., 10 µF) improve transient response under pulsed load conditions typical in LCD backlight modulation.
Does TPS65110RGERG4 support I²C communication for dynamic configuration?
Yes, TPS65110RGERG4 includes CLK and DATA pins compatible with standard I²C protocol (up to 400 kHz), allowing readback of internal status registers and EEPROM-based configuration. However, the device operates in default fixed-output mode without external programming - I²C is optional for diagnostics or advanced sequencing control.
Can TPS65110RGERG4 be used with a 2.4 V input supply?
Yes, TPS65110RGERG4 supports 2.4 V minimum input, but its under-voltage lockout (UVLO) rising threshold is 2.2–2.4 V. To ensure reliable startup, VIN must exceed 2.5 V initially; once enabled, it sustains operation down to 2.4 V. For true 2.4 V cold-start, pre-bias the input rail above UVLO threshold before asserting EN.
What is the thermal pad connection requirement for TPS65110RGERG4?
The exposed thermal pad (Pin 25) of TPS65110RGERG4 must be soldered to a solid PGND copper plane using ≥4 thermal vias (0.3 mm diameter) to inner ground layers. TI recommends a 2.5 mm × 2.5 mm pad area; insufficient thermal relief causes junction temperature to exceed 125°C at full 16 mA VCC load, triggering thermal shutdown.
How does the VCC boost ratio selection work in TPS65110RGERG4?
TPS65110RGERG4 autonomously selects VCC boost ratio (x1.0/x1.33/x1.5/x2.0) by monitoring VIN and VCC feedback. For example, at VIN = 2.8 V, it uses x1.5 to generate 3.3 V; if VIN drops to 2.5 V, it shifts to x2.0. This occurs without external control - ensuring >84% efficiency across battery discharge while maintaining regulated output.
Is TPS65110RGERG4 suitable for new designs given its "Not Recommended for New Designs" status?
While TI classifies TPS65110RGERG4 as "Not Recommended for New Designs", it remains actively manufactured and supported for legacy system refreshes and repair programs. Aetrix Electronics guarantees supply continuity and provides full technical documentation - ideal for sustaining production of fielded PDA, smartphone, and industrial display products.
TPS65110RGERG4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Applications:
- Charge Pump, LTPS LCD
- Voltage - Input:
- 2.4V ~ 5.5V
- Number of Outputs:
- 3
- Voltage - Output:
- -2.7V, 3.3V, 7.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-VQFN (4x4)
TPS65110RGERG4 FAQ
1.How can I place an order for TPS65110RGERG4 through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS65110RGERG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS65110RGERG4 reliable?
The price and inventory of TPS65110RGERG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS65110RGERG4 is usually 5 days.
3.What payment methods are accepted for TPS65110RGERG4?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS65110RGERG4 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS65110RGERG4?
TPS65110RGERG4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS65110RGERG4 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS65110RGERG4?
For technical support, including TPS65110RGERG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS65110RGERG4 requirements.
6.How does Aetrix verify that TPS65110RGERG4 is sourced from the original manufacturer or authorized distributors?
All TPS65110RGERG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS65110RGERG4 meets industry standards.
7.What is the process for return or replacement of TPS65110RGERG4?
All TPS65110RGERG4 units undergo pre-shipment inspection (PSI). If there is an issue with TPS65110RGERG4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS65110RGERG4 part is unused and in its original packaging.
Return procedure for TPS65110RGERG4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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