Texas Instruments TPS65124RGTRG4
- Part No.:
- TPS65124RGTRG4
- Manufacturer:
- Texas Instruments
- Category:
- Special Purpose Regulators
- Package:
- 16-VFQFN Exposed Pad
- Datasheet:
-
TPS65124RGTRG4.pdf
- Description:
- IC REG CONV TFT LCD 4OUT 16QFN
- Quantity:
- Payment:

- Shipping:

Inventory:2,117
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TPS65124RGTRG4 from Texas Instruments is a single-inductor quadruple-output DC-DC converter for a-Si and LTPS TFT-LCD displays, delivering independently regulated VMAIN (3.0–5.3 V/25 mA), VGH (up to +20 V/2 mA), VGL (down to −18 V/2 mA), and programmable power sequencing via ENVGH/ENVGL pins. It operates from 2.7–5.5 V input and achieves up to 83% core efficiency at 4 MHz switching frequency.
For engineers reviewing the TPS65124RGTRG4 datasheet, TPS65124RGTRG4 pinout, TPS65124RGTRG4 application, or TPS65124RGTRG4 equivalent, key selection criteria include its programmable gate-drive sequencing, post-regulated low-ripple VMAIN (5 mVP-P), ±0.8% main output accuracy, and QFN-16 (3 × 3 × 0.9 mm) package with exposed thermal pad.
Technical Context
The TPS65124RGTRG4 uses a free-running variable peak-current PWM control scheme to time-multiplex a single inductor across BOOT, VGH, and VGL outputs, enabling pseudo-fixed-frequency operation at 4 MHz. Its architecture supports fast transient response while maintaining high efficiency across wide input (2.7–5.5 V) and output voltage ranges.
It integrates programmable enable logic for VGH and VGL via dedicated ENVGH and ENVGL pins, allowing independent control of gate-driver power-up/down order. The VMAIN output is post-regulated by an internal LDO to achieve 5 mVP-P ripple, with feedback regulation referenced to 1.213 V at FBM and FBH pins.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.7 V to 5.5 V - supports single-cell Li-ion or dual-cell alkaline input without external regulators |
| VMAIN Output | 3.0 V to 5.3 V / 25 mA - post-regulated LDO stage ensures ≤5 mVP-P ripple for source driver stability |
| VGH Output | Up to +20 V / 2 mA - adjustable via external resistor divider; regulated to ±3% typical accuracy |
| VGL Output | Down to −18 V / 2 mA - independently regulated negative supply with ±3% typical accuracy |
| Switching Frequency | 4.0 MHz - enables use of ultra-thin 8.2 µH or 10 µH inductors and compact PCB layout |
| Power Sequencing | Programmable via ENVGH/ENVGL pins - enables custom gate-drive timing critical for LCD panel reliability |
| Package | 16-pin QFN (3 × 3 × 0.9 mm) with exposed thermal pad - optimized for thermal performance in space-constrained handhelds |
Pinout & Package
TPS65124RGTRG4 is housed in a thermally enhanced 16-pin QFN package (3 mm × 3 mm × 0.9 mm) with an exposed die pad for improved heat dissipation. Pin numbering follows standard top-view orientation with Pin 1 marked by a dot.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| EN (Pin 1) | Enable input | Active-high logic control for main output; must be terminated to avoid floating-induced instability |
| RUN (Pin 2) | Gate driver control | Activates external P-MOSFET for power-down sequencing; pulled down internally via 100 kΩ |
| ENVGL (Pin 3) | VGL enable input | Independent logic control for negative gate supply; required for programmable sequencing in TPS65124 |
| ENVGH (Pin 4) | VGH enable input | Independent logic control for positive gate supply; enables precise startup/shutdown ordering |
| FBL (Pin 5) | VGL feedback input | Connects to VGL–VMAIN resistor divider; regulates to 0 V nominal reference for accurate negative rail |
| FBM (Pin 6) | VMAIN feedback input | Connects to VMAIN resistor divider; regulates to 1.213 V nominal for ±0.8% output accuracy |
| AGND (Pins 3, 4, 7) | Analog ground | Low-noise reference return for feedback networks; must connect to PGND under IC for EMI control |
| VMAIN (Pin 8) | Main output | Post-regulated LDO output for LCD source drivers; delivers low-ripple 3.0–5.3 V at up to 25 mA |
| FBH (Pin 9) | VGH feedback input | Connects to VGH resistor divider; regulates to 1.213 V nominal for ±3% positive rail accuracy |
| VGH (Pin 10) | Positive gate drive output | Boosted output up to +20 V; current-limited to 2 mA for TFT gate line driving |
| BOOT (Pin 11) | Bootstrap supply | Provides gate drive voltage for internal rectifier MOSFET; enables efficient high-side switching |
| PGND (Pin 12) | Power ground | High-current return path for SWP/SWN switches; connects directly to exposed thermal pad |
| SWP (Pin 13) | Low-side switch drain | Connects inductor to ground during switching cycle; handles peak currents up to 200 mA |
| SWN (Pin 14) | High-side switch source | Connects inductor to VIN during switching cycle; monitors inductor current for regulation |
| VIN (Pin 15) | Main input supply | Primary power input (2.7–5.5 V); feeds bias circuitry, control logic, and switching stages |
| GATE (Pin 16) | External MOSFET driver | Drives gate of external P-channel MOSFET for active power-down sequencing |
Key Features
| Feature | Design Value |
|---|---|
| Programmable power sequencing | Dedicated ENVGH and ENVGL pins enable custom gate-drive timing-critical for preventing LCD panel latch-up |
| Post-regulated VMAIN | Integrated LDO reduces VMAIN ripple to ≤5 mVP-P, eliminating need for external filtering in high-resolution displays |
| Single-inductor quadruple output | Time-multiplexes one inductor across BOOT/VGH/VGL, reducing BOM count and PCB area vs. multi-inductor solutions |
| 4 MHz switching frequency | Enables use of 8.2 µH/10 µH ultra-thin inductors (e.g., EPCOS SIMID1812-C), supporting <1 mm profile designs |
| Output short-circuit protection | Internal fault timer (100 µs typ) latches shutdown on VMAIN/VGH/VGL overcurrent, ensuring display system reliability |
| Undervoltage lockout (UVLO) | 2.15 V falling threshold with 100 mV hysteresis prevents erratic operation during battery brownout conditions |
Applications
| Smartphone LCD Power Management | Portable GPS Display Supply |
|---|---|
|
Use Scenario: Powering a 3.5-inch a-Si TFT-LCD panel in a battery-powered smartphone with tight height constraints. IC Role / Device Role / Timing Role: Generates VMAIN (4.5 V), VGH (+15 V), VGL (−12 V), and sequences VGL before VGH to prevent gate oxide stress. Use Value: Single-inductor architecture cuts solution height to <1 mm; 4 MHz switching allows miniature 10 µH inductor placement. |
Use Scenario: Supplying gate and source drivers for a sunlight-readable LTPS TFT display in a handheld GPS unit. IC Role / Device Role / Timing Role: Delivers stable VMAIN (5.0 V/20 mA), VGH (+18 V), VGL (−15 V) with programmable ENVGH/ENVGL timing for cold-start reliability. Use Value: UVLO (2.15 V) ensures operation down to nearly-dead Li-ion cells; 83% efficiency extends battery runtime. |
| Digital Still Camera Backlight Panel | Car Navigation System Display |
|
Use Scenario: Driving a high-contrast 2.7-inch TFT panel in a DSLR camera where EMI must not interfere with image sensor signals. IC Role / Device Role / Timing Role: Provides low-noise VMAIN (3.3 V) with 5 mVP-P ripple and isolated VGH/VGL rails using AGND/PGND separation. Use Value: Post-regulated LDO and dedicated analog ground pins minimize noise coupling into sensitive imaging circuits. |
Use Scenario: Powering a 7-inch automotive-grade TFT display operating across −40°C to +85°C ambient range. IC Role / Device Role / Timing Role: Supplies VMAIN (5.3 V), VGH (+20 V), VGL (−18 V) with guaranteed operation at full spec over temperature. Use Value: Specified performance from −40°C to +85°C and robust short-circuit protection meet AEC-Q100 functional safety expectations. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar TFT-LCD power management applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65123RGT | No ENVGH/ENVGL pins; automatic sequencing only; fixed 3.3 V auxiliary LDO absent | Lacks programmable gate-drive control; suitable only for panels with fixed sequence requirements | Select when sequencing is predefined and board space permits simpler control logic |
| TPS65132A1YFFR | Higher integration: includes I²C interface, telemetry, and wider VMAIN range (2.5–5.5 V); 20-pin WQFN | Supports dynamic voltage scaling and real-time monitoring; requires firmware integration | Choose for advanced systems needing programmable margins, fault logging, or adaptive power control |
Compared with TPS65123RGT, TPS65124RGTRG4 provides design flexibility through independent ENVGH/ENVGL control, while TPS65132A1YFFR adds digital configurability at the cost of increased complexity and footprint-making TPS65124RGTRG4 optimal for cost-sensitive, sequencing-critical handheld displays.
Availability
TPS65124RGTRG4 is available at Aetrix Electronics and suitable for smartphone LCD power management, portable GPS display supply, and digital still camera backlight panel applications requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.
Supply support for TPS65124RGTRG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of experience in display power solutions.
The TPS6512x product line was designed specifically for space-constrained, battery-powered a-Si and LTPS TFT-LCD panels-emphasizing single-inductor efficiency, programmable sequencing, and ultra-low profile packaging.
FAQ
What is the primary function of the ENVGH and ENVGL pins on the TPS65124RGTRG4?
The ENVGH and ENVGL pins on the TPS65124RGTRG4 provide independent logic-level enable control for the VGH and VGL outputs, respectively. Unlike earlier variants (e.g., TPS65120), this enables fully programmable power-up and power-down sequencing-critical for preventing gate oxide damage in TFT-LCD panels. Each pin must be actively driven (not left floating) to ensure stable operation.
Does the TPS65124RGTRG4 include an integrated linear regulator for logic supply?
No, the TPS65124RGTRG4 does not integrate a fixed auxiliary LDO like the TPS65120/121/123. It omits the LDOIN/LDOOUT pins entirely and relies on external logic supplies. This simplifies the die and reduces quiescent current, making it ideal for designs where the timing controller's logic voltage is provided separately.
What is the maximum achievable VMAIN output voltage and its associated current limit?
The TPS65124RGTRG4 supports a VMAIN output range of 3.0 V to 5.3 V. At VMAIN ≤ 5.3 V, the maximum continuous output current is 25 mA; above 5.3 V, the current limit drops to 7.5 mA. This is enforced by the internal LDO stage, which also ensures ≤5 mVP-P ripple and ±0.8% regulation accuracy at the FBM feedback node.
How does the TPS65124RGTRG4 achieve low output ripple on the VMAIN rail?
The TPS65124RGTRG4 achieves ≤5 mVP-P VMAIN ripple through post-regulation: the switching stage first generates a BOOST voltage (VMAIN + ~0.5 V), then feeds it into an integrated low-dropout linear regulator. This LDO filters high-frequency switching noise, eliminating the need for large external ceramic capacitors or ferrite beads in noise-sensitive display applications.
What package type and thermal characteristics does the TPS65124RGTRG4 use?
The TPS65124RGTRG4 uses a 16-pin QFN package (3 mm × 3 mm × 0.9 mm) with an exposed thermal die pad. Its thermal resistance is RθJA = 68°C/W, and it supports derating of 15 mW/°C above 25°C ambient. The exposed pad must be soldered to a thermal plane on the PCB to maintain junction temperature below 135°C under full load.
TPS65124RGTRG4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 16-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Discontinued at Digi-Key
- Applications:
- Converter, TFT LCD
- Voltage - Input:
- 2.5V ~ 5.5V
- Number of Outputs:
- 4
- Voltage - Output:
- 3V ~ 5.6V, Adj up to 20V, Adj down to -18V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-VQFN (3x3)
TPS65124RGTRG4 FAQ
1.How can I place an order for TPS65124RGTRG4 through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS65124RGTRG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS65124RGTRG4 reliable?
The price and inventory of TPS65124RGTRG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS65124RGTRG4 is usually 5 days.
3.What payment methods are accepted for TPS65124RGTRG4?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS65124RGTRG4 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS65124RGTRG4?
TPS65124RGTRG4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS65124RGTRG4 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS65124RGTRG4?
For technical support, including TPS65124RGTRG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS65124RGTRG4 requirements.
6.How does Aetrix verify that TPS65124RGTRG4 is sourced from the original manufacturer or authorized distributors?
All TPS65124RGTRG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS65124RGTRG4 meets industry standards.
7.What is the process for return or replacement of TPS65124RGTRG4?
All TPS65124RGTRG4 units undergo pre-shipment inspection (PSI). If there is an issue with TPS65124RGTRG4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS65124RGTRG4 part is unused and in its original packaging.
Return procedure for TPS65124RGTRG4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TPS65124RGTRG4 Tags

-
TPS51206DSQR
Texas Instruments

-
TPS51200DRCR
Texas Instruments

-
TPS51200DRCT
Texas Instruments

-
TPS62740DSSR
Texas Instruments

-
TPS51100DGQR
Texas Instruments
-
NCP51200MNTXG
onsemi
-
NCP51400MNTXG
onsemi

-
RT9026GSP
Richtek USA Inc.

-
LP2998MRX/NOPB
Texas Instruments

-
TPS51200QDRCRQ1
Texas Instruments

-
DPA423GN-TL
Power Integrations

-
LM10011SD/NOPB
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
