Texas Instruments TPS65132A0YFFR
- Part No.:
- TPS65132A0YFFR
- Manufacturer:
- Texas Instruments
- Category:
- Special Purpose Regulators
- Package:
- 15-UFBGA, DSBGA
- Datasheet:
-
TPS65132A0YFFR.pdf
- Description:
- IC REG TFT/LCD CONV 2OUT 15DSBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
TPS65132A0YFFR from Texas Instruments is a single-inductor, dual-output power supply IC designed for bipolar LCD display bias rails. It delivers +5.0 V / 40 mA and –5.0 V / 40 mA from a 2.5 V–5.5 V input, uses I²C programmability for sequencing and voltage selection, and integrates a synchronous boost converter with LDO and negative charge pump in a 15-ball DSBGA (2.11 mm × 1.51 mm) package - deployed in smartphone and tablet display power systems.
For engineers reviewing the TPS65132A0YFFR datasheet, TPS65132A0YFFR pinout, TPS65132A0YFFR application, or TPS65132A0YFFR equivalent, key selection criteria include its pre-programmed ±5.0 V outputs, 40 mA per rail current capability, I²C-configurable power-up/down sequencing, active discharge control, and compact CSP footprint optimized for space-constrained portable displays.
Technical Context
The TPS65132A0YFFR implements a single-inductor topology where a synchronous boost converter generates an intermediate regulated voltage (REG), which feeds both a low-dropout linear regulator (LDO) for VPOS and a negative charge pump (CPN) for VNEG. Its I²C interface enables dynamic configuration of output voltages, sequencing order, and active discharge behavior - critical for managing display driver startup transients and ESD-safe shutdown.
It operates across –40°C to +85°C ambient, supports standard- and fast-mode I²C (100 kHz / 400 kHz), features undervoltage lockout (UVLO) with 2.5 V rising threshold and 40 ms delay for noise immunity, and delivers >85% efficiency at >10 mA load and >90% at >40 mA - achieved via PFM/CCM mode switching and internal compensation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.5 V to 5.5 V - supports single-cell Li-ion, Li-polymer, and fixed 3.3 V/5 V rails without external regulators. |
| VPOS Output | +5.0 V ±1% - factory-programmed, LDO-regulated positive rail for source driver ICs requiring low-noise bias. |
| VNEG Output | –5.0 V ±1% - factory-programmed, charge-pump-derived negative rail for gate driver bias in AMOLED/LCD panels. |
| Max Output Current | 40 mA per rail - sufficient for small-to-medium display panels; avoids thermal derating in 15-ball CSP package. |
| Efficiency | >90% at IOUT > 40 mA - minimizes heat generation and extends battery life in portable applications. |
| I²C Interface | Standard/fast mode (100/400 kHz) - enables real-time sequencing control, voltage reprogramming, and discharge activation during system sleep/wake cycles. |
| Package | DSBGA-15 (YFF), 2.11 mm × 1.51 mm - ultra-compact footprint compatible with high-density mobile PCB layouts. |
Pinout & Package
TPS65132A0YFFR is housed in a 15-ball DSBGA (YFF) package with 0.4 mm pitch and bottom-side solder balls. Thermal performance is characterized by RθJA = 76.5°C/W and RθJB = 44°C/W, supporting operation up to +85°C ambient.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AGND | Analog ground | Reference node for internal analog blocks; must be connected to low-noise system AGND plane. |
| CFLY1, CFLY2 | Flying capacitor terminals | Connect external 2.2 µF X7R capacitors to enable charge-pump inversion for VNEG generation. |
| ENP | VPOS enable input | Active-high digital control for LDO output; used in I²C-sequenced power-up/down of positive rail. |
| ENN | VNEG enable input | Active-high digital control for charge-pump output; allows independent rail enable/disable timing. |
| OUTP | VPOS output | Delivers +5.0 V / 40 mA to display source drivers; requires 4.7 µF ceramic output capacitor. |
| OUTN | VNEG output | Delivers –5.0 V / 40 mA to display gate drivers; requires 4.7 µF ceramic output capacitor. |
| PGND | Power ground | High-current return path for boost switch and charge pump; must be tied to low-impedance PGND plane. |
| REG | Boost converter output | Intermediate regulated voltage feeding both LDO and CPN; not user-accessible as system output. |
| SCL, SDA | I²C interface | Two-wire serial bus for configuring sequencing, voltage trim, discharge behavior, and status readback. |
| SW | Boost switch node | Internal MOSFET drain connection; requires 4.7 µH inductor and proper layout to minimize EMI. |
| VIN | Main input supply | Accepts 2.5–5.5 V; powers all internal circuitry and supplies energy to boost stage via integrated FETs. |
Key Features
| Feature | Design Value |
|---|---|
| Single-inductor dual-rail architecture | Reduces BOM count by eliminating separate inductors for VPOS/VNEG - cuts solution size by ~30% vs discrete solutions. |
| Factory-programmed ±5.0 V outputs | Eliminates need for external resistor dividers or I²C initialization at boot - ensures deterministic startup in display subsystems. |
| I²C-programmable sequencing | Enables precise control over VPOS/VNEG enable timing and discharge activation - prevents latch-up during panel reset sequences. |
| Active output discharge | Discharges VPOS/VNEG to GND within milliseconds upon disable - meets ESD safety requirements for display interfaces. |
| UVLO with 40 ms delay (A-series) | Rejects short battery voltage dips during RF transmission or motor actuation - prevents unintended rail collapse in handheld devices. |
Applications
| Smartphone Display Bias | Tablet LCD Panel Power |
|---|---|
|
Use Scenario: Supplying gate and source driver bias voltages for 5–10 inch TFT-LCD panels in battery-powered tablets. IC Role / Device Role / Timing Role: Dual-rail power manager generating synchronized +5.0 V and –5.0 V with I²C-controlled startup sequencing to avoid panel flicker during wake-from-sleep. Use Value: Compact 15-ball CSP footprint fits tight bezel areas; >90% efficiency at 40 mA load extends usable screen-on time per charge cycle. |
Use Scenario: Providing stable split-rail bias for high-resolution AMOLED displays in premium smartphones. IC Role / Device Role / Timing Role: Pre-programmed ±5.0 V generator with active discharge ensuring safe, rapid panel power-down during incoming call interruption. Use Value: Factory-set outputs eliminate calibration overhead; 1% output accuracy maintains consistent pixel brightness across temperature range. |
| Wearable Smartwatch Display | Differential Audio Amplifier Bias |
|
Use Scenario: Powering segmented or monochrome LCDs in compact wearable form factors with strict height and thermal constraints. IC Role / Device Role / Timing Role: Ultra-small DSBGA-15 power IC delivering ±5.0 V at 40 mA while maintaining <1.5 mm profile including capacitors. Use Value: 76.5°C/W junction-to-ambient thermal resistance enables full-rated operation in sealed watch enclosures without heatsinking. |
Use Scenario: Generating precision ±5.0 V rails for low-noise headphone amplifiers in portable audio DACs. IC Role / Device Role / Timing Role: Low-ripple dual-output supply using LDO-filtered VPOS and charge-pump VNEG to minimize THD+N in audio signal paths. Use Value: LDO post-regulation reduces boost ripple by >40 dB; 1% output accuracy ensures matched gain in differential amplifier stages. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-rail power management applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65132A YFFR | Identical pinout and package; differs only in pre-programmed VPOS/VNEG (±5.4 V vs ±5.0 V) and default active discharge behavior. | Used where higher bias voltage margin is required for larger display panels or extended temperature operation. | Select TPS65132A0YFFR when ±5.0 V matches display driver datasheet requirements and tighter voltage tolerance is preferred. |
| TPS65132B0YFFR | Same ±5.0 V outputs and 40 mA rating, but features ultra-low shutdown current (130 nA vs 30 µA) and slow-start discharge timing. | Preferred in always-on wearable sensors or IoT nodes where quiescent power dominates battery lifetime calculations. | Choose TPS65132B0YFFR only if sub-µA shutdown current is mandatory; otherwise TPS65132A0YFFR offers better transient response and faster sequencing. |
Compared with TPS65132A0YFFR, the TPS65132A YFFR provides higher output voltage headroom at identical current capability, while TPS65132B0YFFR trades faster startup and stronger discharge drive for nanowatt-level quiescent consumption - making TPS65132A0YFFR optimal for balanced performance in mainstream portable displays.
Availability
TPS65132A0YFFR is available at Aetrix Electronics and suitable for smartphone display bias, tablet LCD power, wearable smartwatch panels, and differential audio amplifier supply applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for TPS65132A0YFFR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and power management technologies, with decades of leadership in high-efficiency DC/DC conversion and display power solutions.
The TPS65132 family was engineered specifically for compact, battery-powered display systems - integrating boost, LDO, and charge-pump topologies into a single chip to replace multi-component discrete bias supplies in smartphones, tablets, and wearables.
FAQ
What output voltages does the TPS65132A0YFFR provide?
The TPS65132A0YFFR is factory-programmed to deliver +5.0 V on the OUTP pin and –5.0 V on the OUTN pin, each with ±1% accuracy over –40°C to +85°C ambient temperature. These values are fixed and cannot be altered via I²C; they match common display driver IC requirements for medium-size LCD and AMOLED panels.
Does the TPS65132A0YFFR require external inductors or capacitors?
Yes, the TPS65132A0YFFR requires an external 4.7 µH inductor between VIN and SW, two 2.2 µF X7R flying capacitors (CFLY1/CFLY2), one 4.7 µF input capacitor (CIN), and two 4.7 µF output capacitors (COUTP/COUTN). The REG pin also needs a 4.7 µF capacitor. All are specified in the TI datasheet Section 7.3.
How does the TPS65132A0YFFR handle power sequencing between VPOS and VNEG?
The TPS65132A0YFFR supports I²C-programmable sequencing via ENP and ENN pins. By default, it enables VPOS first, then VNEG, with configurable delays. Sequencing can be modified through register writes to meet specific display driver startup timing requirements - preventing latch-up or visual artifacts during panel initialization.
What is the maximum continuous output current per rail for the TPS65132A0YFFR?
The TPS65132A0YFFR delivers up to 40 mA continuously on both VPOS and VNEG rails under typical conditions (TA ≤ 85°C, proper PCB thermal design). It is rated for 80 mA peak per rail in pulsed operation, but sustained 40 mA is the guaranteed specification for stable operation in the 15-ball DSBGA package.
Is the TPS65132A0YFFR pin-compatible with other variants in the TPS65132 family?
Yes, all TPS65132x YFFR variants - including TPS65132A0YFFR, TPS65132AYFFR, and TPS65132B0YFFR - share identical 15-ball DSBGA (YFF) packaging, pin assignment, and mechanical footprint. This allows direct substitution in existing layouts when changing pre-programmed output voltages or discharge characteristics.
TPS65132A0YFFR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 15-UFBGA, DSBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- Converter, TFT LCD
- Voltage - Input:
- 2.5V ~ 5.5V
- Number of Outputs:
- 2
- Voltage - Output:
- ±4V ~ 6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 15-DSBGA
TPS65132A0YFFR FAQ
1.How can I place an order for TPS65132A0YFFR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS65132A0YFFR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS65132A0YFFR reliable?
The price and inventory of TPS65132A0YFFR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS65132A0YFFR is usually 5 days.
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Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS65132A0YFFR?
For technical support, including TPS65132A0YFFR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS65132A0YFFR requirements.
6.How does Aetrix verify that TPS65132A0YFFR is sourced from the original manufacturer or authorized distributors?
All TPS65132A0YFFR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS65132A0YFFR meets industry standards.
7.What is the process for return or replacement of TPS65132A0YFFR?
All TPS65132A0YFFR units undergo pre-shipment inspection (PSI). If there is an issue with TPS65132A0YFFR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS65132A0YFFR part is unused and in its original packaging.
Return procedure for TPS65132A0YFFR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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