Texas Instruments TPS65132BYFFR
- Part No.:
- TPS65132BYFFR
- Manufacturer:
- Texas Instruments
- Category:
- Special Purpose Regulators
- Package:
- 15-UFBGA, DSBGA
- Datasheet:
-
TPS65132BYFFR.pdf
- Description:
- IC REG TFT/LCD CONV 2OUT 15DSBGA
- Quantity:
- Payment:

- Shipping:

Inventory:1,873
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Product details
Overview
TPS65132BYFFR from Texas Instruments is a single-inductor, dual-output power management IC designed for bipolar LCD display bias supplies. It integrates a synchronous boost converter (VREG), an LDO (VPOS = +5.4 V/40 mA), and an inverting charge pump (VNEG = −5.4 V/40 mA) with I²C programmability, 2.5 V–5.5 V input range, and >90% efficiency at ≥40 mA load.
For engineers reviewing the TPS65132BYFFR datasheet, TPS65132BYFFR pinout, TPS65132BYFFR application, or TPS65132BYFFR equivalent, this page delivers verified electrical specs, package mapping to 15-ball DSBGA (YFF), I²C-configurable sequencing, active discharge control, and real-world split-rail use cases in portable displays and analog signal chains.
Technical Context
The TPS65132BYFFR uses a single-inductor topology where the boost converter generates VREG (~6.2 V), which feeds both the integrated LDO (for regulated +5.4 V VPOS) and the negative charge pump (for −5.4 V VNEG). Its current-mode boost operates at 1.35–2.25 MHz with PFM/CCM auto-transition, while the I²C interface (100/400 kHz) controls voltage selection, sequencing order, and active discharge enable/disable per rail.
It supports two output current modes: 40 mA (default for TPS65132Bx variants) and 80 mA, with thermal shutdown (140°C), UVLO (2.3–2.5 V), and separate ENP/ENN enables for independent rail control. The YFF package features 15-ball DSBGA (2.11 mm × 1.51 mm) with dedicated AGND/PGND separation and exposed thermal pad.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.5 V to 5.5 V - Supports single-cell Li-ion, Li-polymer, and fixed 3.3 V/5 V rails without external regulators. |
| VPOS Output | +5.4 V / 40 mA - LDO-regulated positive rail with ±1% accuracy over –40°C to +85°C ambient. |
| VNEG Output | –5.4 V / 40 mA - Inverting charge pump rail with ±1% accuracy and 0.8–1.2 MHz switching frequency. |
| Efficiency | >90% at IOUT ≥ 40 mA - Achieved via PFM/CCM mode switching and synchronous rectification in boost stage. |
| I²C Interface | Standard/Fast mode (100/400 kHz) - Enables dynamic voltage programming, power-up/down sequencing, and non-volatile discharge configuration. |
| Quiescent Current | 0.54 mA - Enables low-power operation in always-on display bias applications. |
| Thermal Protection | 140°C shutdown with 5°C hysteresis - Prevents damage during sustained overload or poor PCB thermal design. |
Pinout & Package
TPS65132BYFFR is housed in a 15-ball, 0.4-mm pitch DSBGA package (YFF), measuring 2.11 mm × 1.51 mm with an exposed thermal pad on the bottom side for enhanced thermal dissipation in space-constrained portable designs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AGND | Analog Ground | Reference node for internal analog circuits; must be connected to quiet ground plane to minimize noise coupling into VPOS/VNEG regulation. |
| CFLY1, CFLY2 | Flying Capacitor Terminals | Connect external 2.2 µF X7R capacitors to implement the negative charge pump; placement symmetry critical for ripple suppression. |
| ENP | VPOS Enable Input | Active-high logic control for LDO output; allows independent sequencing of positive rail relative to VNEG or system host. |
| ENN | VNEG Enable Input | Active-high logic control for charge pump output; enables staggered startup/shutdown to avoid supply contention. |
| OUTP | VPOS Output | Regulated +5.4 V supply for source drivers or op-amp rails; requires 4.7 µF ceramic output capacitor for stability. |
| OUTN | VNEG Output | Regulated –5.4 V supply for gate drivers or differential amplifiers; requires 4.7 µF ceramic output capacitor. |
| PGND | Power Ground | High-current return path for boost switch and charge pump; must be routed separately from AGND and tied at single point. |
| REG | Boost Converter Output | Intermediate ~6.2 V rail feeding both LDO and charge pump; requires 4.7 µF ceramic capacitor and low-ESR layout. |
| SCL, SDA | I²C Interface | Two-wire serial bus for configuring output voltages, sequencing, discharge behavior, and monitoring status registers. |
| SW | Boost Switch Node | Connection to external 4.7 µH inductor; high dv/dt node requiring tight loop area and guard ring to reduce EMI. |
| VIN | Main Input Supply | Accepts 2.5–5.5 V battery or rail; requires 4.7 µF input capacitor placed within 2 mm of VIN and PGND pins. |
Key Features
| Feature | Design Value |
|---|---|
| Single-Inductor Dual-Output Architecture | Reduces BOM count by eliminating second inductor; achieves <1.5 mm² solution size with 4.7 µH inductor and five 4.7 µF ceramics. |
| I²C-Programmable Sequencing | Configures power-up/down order (VPOS-first, VNEG-first, simultaneous) and delay timing via registers-critical for LCD panel stress reduction. |
| Active Rail Discharge | Programmable discharge resistors (70 Ω for VPOS, 20 Ω for VNEG) enable controlled ramp-down of outputs during shutdown-prevents latch-up in downstream analog stages. |
| Ultra-Low Quiescent Current | 0.54 mA IQ enables >100-hour standby in always-on wearable displays powered by coin cells or small Li-ion batteries. |
| High-Accuracy Regulation | ±1% output voltage tolerance across –40°C to +85°C ensures stable gate-source biasing for TFT LCDs and precision op-amp operation. |
Applications
| Smartphone LCD Bias Supply | Wearable Display Power |
|---|---|
|
Use Scenario: Driving source/gate driver ICs in 3–5 inch AMOLED or LTPS LCD panels requiring tightly regulated ±5.4 V rails. IC Role / Device Role / Timing Role: Dual-rail bias generator providing synchronized, sequenced VPOS/VNEG with I²C-controlled soft-start to prevent panel flash or image retention. Use Value: Eliminates discrete boost + inverter + LDO solutions; reduces PCB area by 40% and improves startup repeatability across temperature. |
Use Scenario: Powering compact segmented or monochrome LCDs in smartwatches and fitness trackers with limited battery capacity. IC Role / Device Role / Timing Role: Low-IQ split-rail supply enabling >7-day display runtime on 100 mAh coin cell; supports dynamic voltage scaling via I²C. Use Value: Delivers 40 mA per rail at >90% efficiency down to 2.5 V input-extending usable battery voltage range by 0.3 V versus legacy solutions. |
| Differential Audio Amplifier Supply | Instrumentation Op-Amp Bias |
|
Use Scenario: Generating clean ±5.4 V rails for headphone amplifiers or Class-AB line drivers in portable audio DACs. IC Role / Device Role / Timing Role: Low-noise dual-output regulator with LDO-filtered VPOS and charge-pump VNEG-minimizing PSRR degradation in audio paths. Use Value: 1% output accuracy and <10 mV load regulation ensure THD+N < 0.01% at full output swing; eliminates need for post-regulation filtering. |
Use Scenario: Biasing precision instrumentation amplifiers, ADC drivers, or comparator front-ends in portable medical or test equipment. IC Role / Device Role / Timing Role: High-accuracy, thermally stable split supply enabling <1 LSB INL error in 16-bit SAR ADC systems over industrial temperature range. Use Value: ±1% voltage accuracy and 3.4 mV/A load regulation maintain common-mode rejection >100 dB-critical for µV-level signal integrity. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output bias supply applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65132WRTJR | QFN-20 package (4.0 mm × 3.0 mm); same 5.4 V/40 mA outputs but higher 130 nA shutdown current vs. TPS65132BYFFR's 30 µA. | Preferred for prototyping or higher-power layouts needing thermal relief; less suitable for ultra-compact wearables due to larger footprint. | Select when board space permits larger package and thermal performance outweighs miniaturization goals. |
| MAX17504ATP+T | Non-I²C, fixed ±5.0 V outputs; 150 mA per rail; requires external MOSFETs and compensation components-not a single-chip solution. | Used in industrial HMIs where programmability is unnecessary and higher current is mandatory; lacks sequencing or discharge control. | Choose only if fixed voltages and higher current supersede integration level and digital control requirements. |
Compared with TPS65132WRTJR and MAX17504ATP+T, the TPS65132BYFFR uniquely combines ultra-small DSBGA packaging, I²C configurability, and sub-1% voltage accuracy-making it optimal for production-volume portable displays where size, flexibility, and precision are co-constrained.
Availability
TPS65132BYFFR is available at Aetrix Electronics and suitable for smartphone LCD biasing, wearable display power, differential audio amplifier supplies, and instrumentation op-amp biasing requiring stable component supply across long production lifecycles.
Supply support for TPS65132BYFFR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and power management technologies, with over 50 years of leadership in high-reliability power IC design.
The TPS65132 family was developed specifically for compact, battery-powered bipolar LCD display biasing-emphasizing minimal solution size, I²C configurability, and robust thermal performance in portable consumer electronics.
FAQ
What is the exact output voltage capability of the TPS65132BYFFR?
The TPS65132BYFFR is factory-programmed to deliver +5.4 V on VPOS and –5.4 V on VNEG, each rated for 40 mA continuous output. These values are fixed for the 'B' variant and cannot be altered via I²C; other variants (e.g., TPS65132A, TPS65132T6) offer different pre-programmed voltages including ±5.0 V, ±5.1 V, ±5.2 V, ±5.5 V, and ±5.6 V.
Does the TPS65132BYFFR support higher output current than 40 mA?
No-the TPS65132BYFFR is a 40 mA variant and does not support 80 mA or 150 mA modes. Only the TPS65132T6 (80 mA) and TPS65132S (150 mA) variants enable higher current; attempting to draw >40 mA from the TPS65132BYFFR will trigger overcurrent protection and cause VPOS/VNEG collapse.
What package type and dimensions does the TPS65132BYFFR use?
The TPS65132BYFFR uses the YFF package: a 15-ball, 0.4-mm pitch DSBGA measuring 2.11 mm × 1.51 mm with an exposed thermal pad. This matches the mechanical outline in TI's SLVSBM1H datasheet Section 13.1 and is distinct from the 20-pin QFN (RVC) used by TPS65132W.
Can the TPS65132BYFFR be used without I²C configuration?
Yes-the TPS65132BYFFR operates fully autonomously with default settings: VPOS = +5.4 V, VNEG = –5.4 V, 40 mA mode, and fast startup. I²C is optional and used only to modify sequencing, enable active discharge, or read status registers; basic functionality requires only ENP and ENN asserts.
What is the recommended input capacitor for the TPS65132BYFFR?
Texas Instruments specifies a minimum 4.7 µF X5R or X7R ceramic capacitor at the VIN pin, placed within 2 mm of VIN and PGND. This value ensures stable operation across the 2.5 V–5.5 V input range and suppresses high-frequency switching noise from the boost stage.
TPS65132BYFFR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 15-UFBGA, DSBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- Converter, TFT LCD
- Voltage - Input:
- 2.5V ~ 5.5V
- Number of Outputs:
- 2
- Voltage - Output:
- ±4V ~ 6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 15-DSBGA
TPS65132BYFFR FAQ
1.How can I place an order for TPS65132BYFFR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS65132BYFFR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS65132BYFFR reliable?
The price and inventory of TPS65132BYFFR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS65132BYFFR is usually 5 days.
3.What payment methods are accepted for TPS65132BYFFR?
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4.How is shipping managed for TPS65132BYFFR?
TPS65132BYFFR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS65132BYFFR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS65132BYFFR?
For technical support, including TPS65132BYFFR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS65132BYFFR requirements.
6.How does Aetrix verify that TPS65132BYFFR is sourced from the original manufacturer or authorized distributors?
All TPS65132BYFFR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS65132BYFFR meets industry standards.
7.What is the process for return or replacement of TPS65132BYFFR?
All TPS65132BYFFR units undergo pre-shipment inspection (PSI). If there is an issue with TPS65132BYFFR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS65132BYFFR part is unused and in its original packaging.
Return procedure for TPS65132BYFFR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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