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Texas Instruments TPS65132L0YFFT

Part No.:
TPS65132L0YFFT
Manufacturer:
Texas Instruments
Category:
Special Purpose Regulators
Package:
15-UFBGA, DSBGA
Datasheet:
AetrixTPS65132L0YFFT.pdf
Description:
IC REG TFT/LCD CONV 2OUT 15DSBGA
Quantity:
Payment:
Payment
Shipping:
Shipping

Inventory:1,609

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Product details

Overview

TPS65132L0YFFT from Texas Instruments is a single-inductor, dual-output power supply IC designed for bipolar LCD display bias rails. It delivers programmable +5.0 V / –5.0 V outputs at up to 40 mA per rail, operates from 2.5 V to 5.5 V input (e.g., single-cell Li-ion), and integrates I²C interface for voltage sequencing and active discharge control - deployed in smartphones and wearables.

For engineers reviewing the TPS65132L0YFFT datasheet, TPS65132L0YFFT pinout, TPS65132L0YFFT application, or TPS65132L0YFFT equivalent, key selection criteria include its pre-programmed ±5.0 V outputs, 15-ball DSBGA package, I²C-configurable power-up/down sequencing, 1% output accuracy over –40°C to +85°C, and support for split-rail analog circuitry requiring low-noise, tightly regulated dual supplies.

Technical Context

The TPS65132L0YFFT uses a synchronous boost converter (1.35–2.25 MHz) to generate an intermediate REG voltage, which feeds both an integrated LDO (for VPOS) and a negative charge pump (for VNEG). Its single-inductor architecture minimizes solution size while enabling independent 40 mA current capability on each rail with 100% asymmetry support.

I²C interface enables real-time configuration of power-up/down sequencing, output voltage selection (though TPS65132L0 is factory-set to ±5.0 V), active discharge behavior, and soft-start timing. Undervoltage lockout (2.3–2.5 V threshold) and thermal shutdown (140°C) ensure robust operation under battery sag or overload conditions.

Key Specifications

Parameter Value and Actual Design Meaning
Input Voltage Range 2.5 V to 5.5 V - supports direct connection to single-cell Li-ion, Li-polymer, or fixed 3.3 V/5 V rails without external regulators.
VPOS Output Voltage +5.0 V (pre-programmed) - factory-trimmed LDO output with ±1% accuracy across –40°C to +85°C for stable source driver biasing.
VNEG Output Voltage –5.0 V (pre-programmed) - integrated negative charge pump output with ±1% accuracy, eliminating need for external inverting converters.
Max Output Current 40 mA per rail - sufficient for small- to medium-size LCD biasing; enables compact layout with minimal external components.
Efficiency >90% at IOUT > 40 mA - achieved via PFM/CCM mode switching and synchronous rectification, reducing thermal load in space-constrained devices.
I²C Interface Standard/Fast mode (100/400 kHz) - allows dynamic sequencing control, active discharge enable/disable, and register-based diagnostics without additional GPIOs.
Package 15-ball DSBGA (2.11 mm × 1.51 mm) - ultra-compact footprint optimized for thin mobile and wearable PCBs with fine-pitch assembly.

Pinout & Package

TPS65132L0YFFT is housed in a 15-ball DSBGA (YFF) package with 0.4-mm pitch, optimized for minimal board area and low thermal resistance (RθJA = 76.5°C/W).

Pin/Terminal Circuit Role Design Meaning
AGND Analog ground Reference node for internal analog circuits; must be connected to quiet analog ground plane to maintain 1% output accuracy.
CFLY1, CFLY2 Flying capacitor terminals Connect external 2.2 µF X7R capacitors to enable charge-pump-based VNEG generation; placement critical for EMI suppression.
ENP VPOS enable input Active-high logic control for LDO output; used with ENN to implement independent power sequencing of ±5.0 V rails.
ENN VNEG enable input Active-high logic control for negative charge pump; allows staggered startup/shutdown to prevent latch-up in display drivers.
OUTP Positive output Delivers regulated +5.0 V to LCD source drivers; requires 4.7 µF ceramic output capacitor for stability and transient response.
OUTN Negative output Delivers regulated –5.0 V to LCD gate drivers; decoupled with 4.7 µF ceramic capacitor to minimize ripple-induced crosstalk.
REG Boost converter output Intermediate regulated voltage feeding both LDO and charge pump; not user-accessible but critical for internal efficiency optimization.
SCL, SDA I²C interface signals Enable firmware-controlled configuration of discharge behavior, sequencing order, and fault monitoring without hardware changes.
VIN Main input supply Accepts 2.5–5.5 V; connects directly to battery or system rail; internal UVLO ensures safe start-up only above 2.3 V.

Key Features

Feature Design Value
Single-inductor dual-output topology Reduces BOM count by eliminating second inductor; achieves <12 mm² total solution size including all passives.
±1% output voltage accuracy Maintains display contrast and grayscale fidelity across temperature and load; eliminates need for external trimming or calibration.
I²C-programmable sequencing Enables precise control of VPOS/VNEG power-up order (e.g., VNEG before VPOS) to prevent display panel damage during initialization.
Active output discharge Programmable discharge resistors (70 Ω on VPOS, 20 Ω on VNEG) safely bleed stored energy during shutdown, meeting fast-power-down requirements.
PFM/CCM light-load efficiency Extends battery life in standby mode: >85% efficiency at 10 mA, >90% at 40 mA, with no audible switching noise.

Applications

Smartphone LCD Bias Supply Wearable Display Power

Use Scenario: Powering source and gate driver ICs in 3–5 inch AMOLED/LCD panels within slim smartphone bezels.

IC Role / Device Role / Timing Role: Generates tightly regulated ±5.0 V rails with controlled sequencing to avoid panel latch-up during boot and sleep transitions.

Use Value: Eliminates discrete DC/DC converters and reduces solution height to <0.6 mm - critical for mechanical stack-up constraints.

Use Scenario: Supplying dual-rail op-amps and sensor signal chains in smartwatches with coin-cell or micro-battery sources.

IC Role / Device Role / Timing Role: Delivers low-noise ±5.0 V from 3.0 V input while maintaining >90% efficiency at 20 mA load for extended runtime.

Use Value: Enables high PSRR analog front-ends without dedicated LDOs; I²C configurability supports firmware-driven power states.

Differential Audio Amplifier Bias Instrumentation Op-Amp Supply

Use Scenario: Providing symmetrical supply rails for Class-AB headphone amplifiers in portable media players.

IC Role / Device Role / Timing Role: Supplies matched ±5.0 V with <1% tracking error to minimize even-order harmonic distortion in audio paths.

Use Value: Replaces dual isolated buck converters; single-inductor design cuts EMI emissions by >10 dB compared to discrete solutions.

Use Scenario: Powering precision instrumentation amplifiers and ADC reference buffers in handheld test equipment.

IC Role / Device Role / Timing Role: Delivers low-drift ±5.0 V with 1% accuracy and <3.4 mV/A load regulation for sub-16-bit measurement integrity.

Use Value: Maintains analog performance across battery discharge curve; active discharge prevents residual voltage from corrupting zero-scale readings.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-output bias supply applications.

Alternative Part Technical Difference Application Difference Selection Advice
TPS65132A0YFFT Same ±5.0 V outputs and YFF package, but features FAST startup (no 40-ms delay) and higher shutdown current (30 µA vs. 130 nA). Better suited for systems requiring immediate power-on after wake-up; less optimal for ultra-low-quiescent battery monitoring. Select TPS65132A0YFFT if fast wake-up latency is prioritized over lowest possible shutdown current.
TPS65132B2YFFT Pre-programmed to ±5.2 V, same 40 mA rating, but implements SLOW active discharge and 500 µs LDO soft-start (vs. 140 µs in A-series). Designed for applications needing tighter voltage margin against overvoltage stress on display ICs; slower ramp reduces inrush in high-capacitance panels. Choose TPS65132B2YFFT when panel specifications require >5.0 V headroom or when soft-start duration must exceed 200 µs.

Compared with TPS65132L0YFFT, TPS65132A0YFFT offers faster wake-up at the cost of higher shutdown current, while TPS65132B2YFFT provides higher output voltage and longer soft-start - making TPS65132L0YFFT the optimal choice for standard ±5.0 V LCD bias where ultra-low quiescent current and balanced timing are required.

Availability

TPS65132L0YFFT is available at Aetrix Electronics and suitable for smartphone displays, wearable electronics, differential audio systems, and precision instrumentation requiring stable component supply with full traceability and long-term lifecycle support.

Supply support for TPS65132L0YFFT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in battery-powered and space-constrained applications.

The TPS65132 family was developed specifically for compact, high-efficiency dual-rail power in portable displays - integrating boost, LDO, and charge pump functions into a single chip to replace multi-component solutions in smartphones, tablets, and wearables.

FAQ

What output voltages does the TPS65132L0YFFT deliver?

The TPS65132L0YFFT is factory-programmed to deliver +5.0 V on the VPOS rail and –5.0 V on the VNEG rail, with ±1% accuracy over –40°C to +85°C. These values are fixed and cannot be altered via I²C; alternative variants like TPS65132B2YFFT offer ±5.2 V, while TPS65132T6YFFT provides ±5.6 V.

Does the TPS65132L0YFFT support I²C configuration despite being pre-programmed?

Yes, the TPS65132L0YFFT retains full I²C functionality for configuring power-up/down sequencing order, enabling/disabling active discharge on VPOS and VNEG, setting soft-start timing, and reading status registers - even though its ±5.0 V outputs are fixed at factory. This enables flexible system-level power management without changing hardware.

What is the maximum supported output current for each rail of the TPS65132L0YFFT?

The TPS65132L0YFFT supports up to 40 mA on both the VPOS (+5.0 V) and VNEG (–5.0 V) rails simultaneously. It does not support the 80 mA or 150 mA modes found in other variants like TPS65132T6YFFT or TPS65132SYFFT - those require different part numbers and distinct internal current-limit settings.

Which external components are mandatory for stable operation of the TPS65132L0YFFT?

Mandatory external components for the TPS65132L0YFFT include: one 4.7 µF input capacitor (X7R), two 4.7 µF output capacitors (one each on OUTP and OUTN), one 2.2 µF flying capacitor (CFLY1/CFLY2), and one 4.7 µH inductor on the SW–REG path. Omitting any of these compromises regulation accuracy, efficiency, or EMI performance.

How does the TPS65132L0YFFT handle power sequencing between VPOS and VNEG rails?

The TPS65132L0YFFT uses separate enable pins (ENP for VPOS, ENN for VNEG) and I²C-controlled sequencing registers to implement programmable startup and shutdown order. For example, setting ENN HIGH before ENP ensures VNEG powers up first - preventing reverse biasing of display panel diodes and avoiding latch-up in source/gate driver ICs.

TPS65132L0YFFT Specifications

Product attributes
Attribute value
Manufacturer:
Texas Instruments
Series:
-
Package/Case:
15-UFBGA, DSBGA
Packaging:
Tape & Reel (TR)
Product Status:
Active
Applications:
Converter, TFT LCD
Voltage - Input:
2.5V ~ 5.5V
Number of Outputs:
2
Voltage - Output:
±4V ~ 6V
Operating Temperature:
-40°C ~ 85°C (TA)
Grade:
-
Qualification:
-
Mounting Type:
Surface Mount
Supplier Device Package:
15-DSBGA

TPS65132L0YFFT FAQ

1.How can I place an order for TPS65132L0YFFT through Aetrix?

Please submit a Request for Quotation (RFQ) for TPS65132L0YFFT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for TPS65132L0YFFT reliable?

The price and inventory of TPS65132L0YFFT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS65132L0YFFT is usually 5 days.

3.What payment methods are accepted for TPS65132L0YFFT?

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TPS65132L0YFFT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your TPS65132L0YFFT order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for TPS65132L0YFFT?

For technical support, including TPS65132L0YFFT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS65132L0YFFT requirements.

6.How does Aetrix verify that TPS65132L0YFFT is sourced from the original manufacturer or authorized distributors?

All TPS65132L0YFFT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS65132L0YFFT meets industry standards.

7.What is the process for return or replacement of TPS65132L0YFFT?

All TPS65132L0YFFT units undergo pre-shipment inspection (PSI). If there is an issue with TPS65132L0YFFT, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The TPS65132L0YFFT part is unused and in its original packaging.

Return procedure for TPS65132L0YFFT:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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