Texas Instruments TPS65160APWP

Overview

TPS65160APWP from Texas Instruments is a highly integrated bias power supply IC for TFT LCD panels, delivering four regulated outputs: VS (up to 17.5 V), VLOGIC (1.8–5.0 V), VGH (+23 V/50 mA), and VGL (−5 V/50 mA). It integrates a 1.5-A step-down converter, a 1.5-A boost converter, and dual charge-pump drivers in a single HTSSOP-28 package with PowerPAD™ thermal enhancement. Designed for LCD TV and monitor applications requiring precise voltage sequencing and high-current panel biasing.

For engineers reviewing the TPS65160APWP datasheet, TPS65160APWP pinout, TPS65160APWP application, or TPS65160APWP equivalent, this device supports adjustable power-on sequencing (via DLY1/DLY2), 500/750 kHz selectable switching frequency (FREQ pin), overvoltage protection (19.5 V on VS), and gate drive output (GD) for external MOSFET isolation - critical for robust TFT panel power management.

Technical Context

The TPS65160APWP implements a voltage-mode PWM architecture with input voltage feedforward for both its main boost and step-down converters, enabling tight line/load regulation (0.037%/A load regulation on VLOGIC). Its dual charge-pump drivers use internal current sources/sinks with external flying capacitors to generate regulated positive (VGH) and negative (VGL) bias rails, each with independent feedback (FBP/FBN) and drive pins (DRP/DRN).

Sequencing is controlled via EN1 (enables buck + VGL), EN2 (enables boost + VGH), and two programmable delay timers (DLY1, DLY2) that accept external capacitors to set timing between output ramps. The GD open-drain output latches low when VS reaches ±8% of regulation, providing fail-safe control of external isolation switches.

Key Specifications

Pinout & Package

TPS65160APWP is housed in a thermally enhanced 28-pin HTSSOP package (PWP) with exposed PowerPAD™ soldered to PGND for optimal thermal performance. Pin count and layout match TI's TPS65160 family, supporting drop-in compatibility within the A-variant series.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar TFT LCD bias power supply applications.

Compared with TPS65160PWP, the TPS65160APWP offers tighter OVP (19.5 V vs. 23 V) and lower UVLO (8.8 V vs. 6.4 V), improving safety margin and brownout resilience. Versus TPS65161APWP, it omits VCOM generation but reduces cost and thermal load where VCOM is supplied externally.

Availability

TPS65160APWP is available at Aetrix Electronics and suitable for LCD TV panel biasing, monitor timing controller (TCON) power, and industrial HMI display applications requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.

Supply support for TPS65160APWP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with over 50 years of innovation in high-reliability power conversion solutions.

The TPS65160A product line was designed specifically for TFT LCD panel biasing in consumer and industrial displays, integrating multiple DC/DC functions with precise sequencing and protection features to replace discrete power trees.

FAQ

What is the maximum allowable input voltage for the TPS65160APWP?

The TPS65160APWP supports an input voltage range of 9.2 V to 14 V, with undervoltage lockout (UVLO) releasing at 8.8 V (typical) when VIN rises. Absolute maximum rating on VIN is 16.5 V, but operation above 14 V violates recommended conditions and may compromise reliability or regulation accuracy. Always maintain input within the 9.2–14 V window for full specification compliance in designs using the TPS65160APWP.

How does the TPS65160APWP implement power-on sequencing between VLOGIC, VGL, VS, and VGH?

The TPS65160APWP uses EN1 and EN2 enable inputs along with DLY1 and DLY2 timing pins to control sequencing. EN1 activation starts the step-down converter (VLOGIC); DLY1 then delays VGL ramp-up. EN2 activation starts the boost converter (VS) and positive charge pump (VGH); DLY2 delays their ramp after VLOGIC regulation is confirmed. Each delay is set by an external capacitor sinking 4.8 µA - a 10 nF cap yields ~2.1 ms delay. This ensures safe, controlled startup in the TPS65160APWP.

What is the function of the GD pin on the TPS65160APWP, and how is it used?

The GD (gate drive) pin on the TPS65160APWP is an open-drain output that latches low when the VS output reaches ±8% of its regulated value. It remains low until EN2 is cycled low, providing fail-safe control of an external MOSFET placed in series with VS or VGH. This prevents unregulated voltage from reaching sensitive panel circuitry during startup, fault, or shutdown - a key safety feature implemented directly in the TPS65160APWP.

Can the TPS65160APWP generate VGH and VGL simultaneously, and what external components are required?

Yes, the TPS65160APWP generates VGH and VGL simultaneously using dedicated positive and negative charge-pump drivers. For VGH: connect DRP to flying capacitor (Cfly), FBP to resistor divider, and SUP to VIN or VS (≤15 V). For VGL: connect DRN to flying capacitor/diode network, FBN to resistor divider, and use two Schottky diodes (e.g., BAT54). Both require external resistors (R3/R4 for VGL; R5/R6 for VGH) to set output voltage based on the 1.213 V internal reference - fully supported in the TPS65160APWP.

What thermal management considerations apply to the TPS65160APWP in continuous operation?

The TPS65160APWP uses an HTSSOP-28 package with PowerPAD™ thermally connected to PGND. At 85°C ambient, its maximum power dissipation is 1.42 W. To maintain junction temperature ≤125°C, design a low-thermal-resistance PGND plane (≥200 mm² copper), use ≥4 thermal vias under the PowerPAD™, and avoid enclosing the device. Derate output currents if ambient exceeds 70°C - the TPS65160APWP's thermal shutdown activates at 155°C with 5°C hysteresis to prevent permanent damage.