Texas Instruments TPS65160PWP

Overview

TPS65160PWP from Texas Instruments is a highly integrated bias power supply IC for TFT LCD panels, featuring a 1.5-A step-down converter (VLOGIC), a 1.5-A boost converter (VS up to 20 V), and dual regulated charge-pump drivers (VGH = +23 V/50 mA, VGL = −5 V/50 mA). It operates from 8–14 V input, includes adjustable soft-start, overvoltage protection (23 V), and 500/750 kHz selectable switching frequency - enabling compact, high-efficiency panel power in LCD TVs and monitors.

For engineers reviewing the TPS65160PWP datasheet, TPS65160PWP pinout, TPS65160PWP application, or TPS65160PWP equivalent, this page delivers verified functional identity, validated HTSSOP-28 pin mapping, confirmed sequencing control via EN1/EN2/DLY1/DLY2, real-world efficiency curves, and two rigorously cross-checked alternative parts for TFT LCD bias supply designs.

Technical Context

The TPS65160PWP integrates four independent regulated outputs: a voltage-mode boost converter (VS) with internal 2.8-A N-MOSFET switch and 23-V overvoltage protection; a nonsynchronous step-down converter (VLOGIC) with 1.5-A rating and bootstrap gate drive; and dual charge-pump drivers - one positive (VGH) and one negative (VGL) - each with external resistor-programmable output and dedicated drive pins (DRP/DRN).

Sequencing is implemented via dual enable inputs (EN1 for buck/VGL; EN2 for boost/VGH) and two delay-setting pins (DLY1, DLY2) that accept external capacitors to define startup timing between outputs. The FREQ pin selects fixed 500 kHz or 750 kHz operation across all converters, while GD provides an open-drain gate-drive signal latched low when VS reaches regulation.

Key Specifications

Pinout & Package

TPS65160PWP is housed in a thermally enhanced HTSSOP-28 (PWP) package with exposed PowerPAD™ soldered to PGND. Pin numbering follows standard TI HTSSOP layout; Pin 1 is FB (boost feedback), Pin 28 is SS (soft-start), and Pins 6/7 are PGND. The PowerPAD must be electrically and thermally connected to system ground plane.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar TFT LCD bias supply applications.

Compared with TPS65160PWP, TPS65161APWPR offers reduced VS headroom but tighter OVLO for cost-sensitive consumer panels, while RTQ2132B-QT provides automotive qualification at the expense of sequenced startup control and pin compatibility.

Availability

TPS65160PWP is available at Aetrix Electronics and suitable for LCD TV power subsystems, monitor bias supply designs, and industrial HMI display applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for TPS65160PWP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in display power solutions.

The TPS65160 product line was designed specifically to consolidate TFT LCD panel bias power into a single IC for cost-sensitive, space-constrained consumer and industrial displays - targeting 12-V input systems with strict sequencing and protection requirements.

FAQ

What is the maximum allowable input voltage for TPS65160PWP?

The absolute maximum input voltage on VIN and SUP pins is 16.5 V, but the recommended operating range is 8 V to 14 V per datasheet specifications. Exceeding 14 V risks violating the 23-V overvoltage protection threshold on the VS output and may trigger premature shutdown. For reliable operation in 12-V systems, TPS65160PWP maintains full functionality across line and load variations without derating.

How does the GD pin function in TPS65160PWP?

The GD pin on TPS65160PWP is an open-drain gate-drive output that goes low-impedance when the main boost converter output VS reaches regulation (within 8% of target), and returns to high-impedance only when EN2 is cycled low. It is designed to drive the gate of an external N-channel MOSFET in series with VS or VGH, enabling input-to-output isolation during fault conditions or power sequencing.

Can TPS65160PWP generate both positive and negative bias voltages simultaneously?

Yes, TPS65160PWP simultaneously generates +23 V (VGH) and −5 V (VGL) using its integrated positive and negative charge-pump drivers. Each uses dedicated drive pins (DRP/DRN), feedback inputs (FBP/FBN), and external components - including Schottky diodes for VGL - to deliver regulated, sequenced outputs essential for TFT LCD gate driver operation.

What package type and thermal requirements apply to TPS65160PWP?

TPS65160PWP uses the HTSSOP-28 (PWP) package with an exposed PowerPAD™ that must be soldered to a PGND copper pour for thermal and electrical integrity. At 25°C ambient, its maximum power dissipation is 3.57 W; derating to 1.42 W is required at 85°C ambient. Thermal resistance θ_JA is 28°C/W when PowerPAD is properly connected.

How is power-on sequencing controlled in TPS65160PWP?

TPS65160PWP implements sequencing via two enable inputs (EN1 for buck/VGL; EN2 for boost/VGH) and two delay pins (DLY1, DLY2). Connecting capacitors to DLY1 and DLY2 sets precise delays - e.g., 10 nF yields ~2.3 ms delay - between VLOGIC turn-on and subsequent VGL or VS/VGH activation, preventing panel damage from improper voltage ramp order.