Texas Instruments TPS65197BRUYT

Overview

TPS65197BRUYT from Texas Instruments is an 8-channel LCD timing controller level-shifter IC for gate-in-panel (GIP) displays, supporting STV/RESET and six CLK outputs with selectable 0-/2-/3-channel charge-sharing, VGH up to 45 V, VGL down to –20 V, and panel discharge via DISCH1/DISCH2 during shutdown. It operates in notebook, monitor, and TV display systems requiring precise high-voltage logic translation.

For engineers reviewing the TPS65197BRUYT datasheet, TPS65197BRUYT pinout, TPS65197BRUYT application, or TPS65197BRUYT equivalent, key selection criteria include its 28-pin WQFN package, latch-based shutdown detection, T-CON failure detection logic (TPS65197 variant), and compatibility with 100-kHz clock inputs and 150-pF capacitive loads.

Technical Context

The TPS65197BRUYT implements dual negative supplies (VGL1/VGL2) and a single positive supply (VGH) to drive eight level-shifted outputs: STVOUT, RESETOUT, and six CLKOUTx channels. Its internal charge-sharing logic-configured by SEL_CS voltage-is latched at VGH UVLO threshold crossing and supports three modes: disabled, 2-channel (CLKOUT1↔CLKOUT3↔CLKOUT5 and CLKOUT2↔CLKOUT4↔CLKOUT6), or 3-channel (CLKOUT1↔CLKOUT4, CLKOUT2↔CLKOUT5, CLKOUT3↔CLKOUT6).

During power-down, DIS_SENSE < 1.26 V triggers latched discharge mode: all CLKOUTx and DISCH1/DISCH2 outputs are pulled to VGH until VGH falls below 3.5 V, while STVOUT/RESETOUT retain level-shifting behavior. The device includes undervoltage lockout (13.5–16.5 V rising, 2–5 V falling) and thermal shutdown (130–170 °C), with outputs forced to high-impedance upon thermal fault.

Key Specifications

Pinout & Package

TPS65197BRUYT is housed in a 28-pin WQFN (RUY) package, 4.00 mm × 4.00 mm, with exposed thermal pad connected internally to VGL1. The package supports high-power dissipation via multi-layer copper plane connection through ≥6 vias to a ≥10 cm² VGL1 ground plane.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LCD level-shifting applications.

Compared with TPS65197BRUYT, TPS65197BRTVR removes frame-synchronized reset but simplifies timing validation, while TPS65195RTVR reduces channel count and eliminates discharge control-making both alternatives viable only when those specific TPS65197BRUYT capabilities are unused in the target design.

Availability

TPS65197BRUYT is available at Aetrix Electronics and suitable for notebook display modules, industrial monitor designs, and broadcast-grade TV panels requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for TPS65197BRUYT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of experience in display interface solutions.

The TPS65197 product line delivers integrated level-shifting and panel discharge for gate-in-panel LCDs, designed specifically to replace discrete HV buffer arrays and simplify timing controller-to-panel interconnect in space-constrained consumer and professional displays.

FAQ

What is the function of the DIS_SENSE pin on the TPS65197BRUYT?

The DIS_SENSE pin on the TPS65197BRUYT is an analog input that monitors discharge readiness. When its voltage falls below 1.17–1.36 V, it triggers latched panel discharge mode: all CLKOUTx, STVOUT, RESETOUT, DISCH1, and DISCH2 outputs are pulled to VGH. This state remains active until VGH drops below 3.5 V, ensuring reliable shutdown sequencing in the TPS65197BRUYT.

How does the TPS65197BRUYT differ from the TPS65197B variant?

The TPS65197BRUYT implements T-CON failure detection via STV pulse-triggered logic reset: CLKOUT1–CLKOUT6 are forced to VGL1 after each STVIN rising edge and released only by the next CLKIN1 rising edge. The TPS65197B omits this behavior-its outputs always follow inputs. This distinction makes the TPS65197BRUYT essential for systems requiring frame-synchronized recovery from T-CON glitches.

What are the supply voltage requirements for the TPS65197BRUYT?

The TPS65197BRUYT requires three independent supplies: VGH from 16.5 V to 45 V (positive rail), VGL1 from –20 V to –3 V (primary negative rail), and VGL2 from –20 V to –3 V (secondary negative rail, less negative than VGL1). VGL1 must remain ≤ VGL2; recommended decoupling is 1 µF ceramic per rail placed within 2 mm of the respective pins.

Can the TPS65197BRUYT support 3-channel charge-sharing and 2-channel charge-sharing simultaneously?

No-the TPS65197BRUYT supports only one charge-sharing mode at a time, selected by the SEL_CS pin voltage: 0–0.5 V disables charge-sharing, 1–2 V enables 3-channel coupling (CLKOUT1↔CLKOUT4, CLKOUT2↔CLKOUT5, CLKOUT3↔CLKOUT6), and 2.8–6.5 V enables 2-channel coupling (CLKOUT1↔CLKOUT3↔CLKOUT5 and CLKOUT2↔CLKOUT4↔CLKOUT6). Mode selection is latched at VGH UVLO crossing and cannot be changed dynamically.

What thermal management practices are required for the TPS65197BRUYT in high-power operation?

The TPS65197BRUYT's exposed thermal pad must be connected via ≥6 vias to a ≥10 cm² copper area referenced to VGL1. Layout guidelines specify wide power traces (≥0.5 mm), 1-µF decoupling capacitors placed within 2 mm of VGH/VGL1 pins, and short, symmetric output traces to minimize EMI and overshoot. Junction temperature must stay below 125 °C for continuous operation; thermal shutdown activates at 130–170 °C.