Texas Instruments TPS65197RUYR

Overview

TPS65197RUYR from Texas Instruments is an 8-channel LCD timing controller level-shifter IC for gate-in-panel (GIP) displays, supporting STV/RESET and six CLK outputs with selectable charge-sharing (none/2-channel/3-channel), panel discharge to VGH during shutdown, and T-CON failure detection. It operates with VGH = 16.5–45 V, VGL1/VGL2 = –20 to –3 V, and supports 100-kHz clock frequency in a 28-pin 4-mm × 4-mm WQFN package.

For engineers reviewing the TPS65197RUYR datasheet, TPS65197RUYR pinout, TPS65197RUYR application, or TPS65197RUYR equivalent, key selection considerations include high-side/low-side on-resistance (11 Ω / 7 Ω for CLKOUTx), slew rate (50–150 V/µs), propagation delay (40–150 ns), UVLO thresholds (13.5–16.5 V rising, 2–5 V falling), and thermal shutdown at 130–170 °C - all critical for notebook, monitor, and TV GIP power sequencing integrity.

Technical Context

The TPS65197RUYR implements dual negative supplies (VGL1, VGL2) and one positive supply (VGH) to drive GIP gate lines, with independent level-shifting paths for STV/RESET (2 channels) and six clock outputs (CLKOUT1–CLKOUT6). Its charge-sharing logic is configured via SEL_CS voltage (0.5 V, 1–2 V, or 2.8–6.5 V) to enable no, 2-channel, or 3-channel coupling between clock pairs.

During power-down, DIS_SENSE < 1.26 V triggers latched shut-down mode where all CLKOUTx and DISCH1/DISCH2 are pulled to VGH; otherwise, outputs follow inputs until VGH falls below 3.5 V. The device includes undervoltage lockout (UVLO) and thermal shutdown (150 °C typical) with latch-and-reset behavior requiring VGH fall below falling UVLO to recover.

Key Specifications

Pinout & Package

TPS65197RUYR is housed in a 28-pin WQFN (RUY) package with 4.00 mm × 4.00 mm body size and exposed thermal pad connected to VGL1. Pin assignment follows TI's standard top-view layout with dedicated input (CLKIN1–CLKIN6, STVIN, RESETIN), output (CLKOUT1–CLKOUT6, STVOUT, RESETOUT, DISCH1, DISCH2), supply (VGH, VGL1, VGL2, GND), and configuration (SEL_CS, DIS_SENSE, CS_1–CS_4) terminals.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LCD level-shifting applications.

Compared with TPS65197RUYR, TPS65197BRUYR removes reset logic for higher signal fidelity in stable T-CON environments, while TPS65195RUYR sacrifices two channels, discharge, and charge-sharing to reduce complexity and cost - making TPS65197RUYR the optimal choice for full-featured GIP timing control with safety-critical shutdown behavior.

Availability

TPS65197RUYR is available at Aetrix Electronics and suitable for notebook, monitor, and TV GIP display designs requiring stable component supply, long-lifecycle support, and guaranteed traceability for industrial and consumer electronics manufacturing.

Supply support for TPS65197RUYR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog and embedded processing technologies, with leadership in power management, signal chain, and high-reliability ICs for industrial, automotive, and consumer markets.

The TPS65197RUYR belongs to TI's LCD power management and timing controller product line, designed specifically to replace discrete level-shifter + discharge-FET solutions in gate-in-panel LCD systems with integrated, sequenced, and fault-protected high-voltage signal translation.

FAQ

What is the primary function of the TPS65197RUYR in LCD display systems?

The TPS65197RUYR serves as an 8-channel level-shifter IC that converts low-voltage timing-controller (T-CON) signals - including STV, RESET, and six clock inputs - into high-voltage gate-drive signals (up to 45 V) required by gate-in-panel (GIP) LCD displays. It integrates charge-sharing, panel discharge, and T-CON failure detection to optimize power, image quality, and reliability. The TPS65197RUYR is essential for notebook, monitor, and TV GIP architectures where compact, integrated timing control is critical.

How does the TPS65197RUYR handle power-down sequencing and panel discharge?

The TPS65197RUYR uses the DIS_SENSE pin to detect shutdown initiation: when DIS_SENSE falls below 1.17–1.36 V, it latches all CLKOUTx, STVOUT, RESETOUT, DISCH1, and DISCH2 to VGH to actively discharge the panel. This state persists until VGH drops below the falling UVLO threshold (~3.5 V), ensuring safe, controlled shutdown. During normal operation, DISCH1 connects to VGL1 and DISCH2 to VGL2. The TPS65197RUYR thus eliminates need for external discharge circuitry while guaranteeing repeatable panel reset behavior.

What are the key differences between TPS65197RUYR and TPS65197BRUYR?

The TPS65197RUYR implements STVIN-triggered logic reset: each STVIN rising edge forces CLKOUT1–CLKOUT6 to VGL1 until the next CLKIN1 rising edge releases them. The TPS65197BRUYR omits this feature and always follows input signals - including at startup. Both share identical pinout, electrical specs, charge-sharing modes, and discharge functionality. Therefore, TPS65197RUYR is preferred where T-CON signal integrity is uncertain and frame-synchronized blanking is needed; TPS65197BRUYR suits deterministic, high-reliability T-CON interfaces.

What supply voltage ranges must be observed for proper operation of the TPS65197RUYR?

The TPS65197RUYR requires three independent supply rails: VGH = 16.5 V to 45 V (positive), VGL1 = –20 V to –3 V (primary negative), and VGL2 = –20 V to –3 V (secondary negative, must be ≥ VGL1). VGL1 must remain more negative than or equal to VGL2 at all times. Startup sequencing mandates VGL1/VGL2 presence before VGH ramp-up, and VGH must rise no faster than 100 µs to avoid UVLO false triggering. All supplies require local 1-µF ceramic decoupling capacitors placed near their respective pins.

How is charge-sharing configured and what benefits does it provide in the TPS65197RUYR?

Charge-sharing in the TPS65197RUYR is selected via the SEL_CS pin voltage: <0.5 V disables it, 1–2 V enables 3-channel coupling (CLKOUT1↔CLKOUT4, CLKOUT2↔CLKOUT5, CLKOUT3↔CLKOUT6), and 2.8–6.5 V enables 2-channel coupling (CLKOUT1↔CLKOUT3↔CLKOUT5, CLKOUT2↔CLKOUT4↔CLKOUT6). This reduces dynamic power consumption by recycling charge between coupled clock lines and improves image uniformity by minimizing voltage droop across large GIP panels - directly enhancing contrast and reducing power supply ripple.