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Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Special Purpose Regulators

Texas Instruments TPS65232A0RHAR

Name: TPS65232A0RHAR
Brand: Texas Instruments
SKU: TPS65232A0RHAR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: TPS65232A0RHAR

Manufacturer:: Texas Instruments

Category:: Special Purpose Regulators

Package:: 40-VFQFN Exposed Pad

Datasheet:: TPS65232A0RHAR.pdf

Description:: IC REG CTRLR/CONV 3OUT 40VQFN

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Product details

Overview

TPS65232A0RHAR from Texas Instruments is a triple-output synchronous buck power management IC integrating one PWM controller and two fully integrated step-down regulators with internal high- and low-side MOSFETs. It delivers 3.3–6.1 V at up to 6 A (BUCK1), 0.9–3.3 V at up to 3 A (BUCK2), and 0.9–3.3 V at up to 3 A (BUCK3), operating from 10.8–22 V input, with 500 kHz/1 MHz switching frequencies and thermal/overcurrent protection. It is used in xDSL modems and wireless access points for multi-rail sequencing.

For engineers reviewing the TPS65232A0RHAR datasheet, TPS65232A0RHAR pinout, TPS65232A0RHAR application, or TPS65232A0RHAR equivalent, key selection factors include its 40-pin QFN package, independent enable-controlled power-up sequencing, adjustable output voltages via external feedback resistors, and integrated current-limit programming via TRIP pin resistor.

Technical Context

The TPS65232A0RHAR implements three independent voltage-mode synchronous buck converters: BUCK1 is a controller-only stage requiring external high- and low-side FETs (e.g., FDS6982), while BUCK2 and BUCK3 integrate both FETs. Each converter uses Type III compensation with internal pole-zero pairs at 45 kHz and 240 kHz to stabilize ceramic-capacitor-based designs without external loop components.

Power sequencing is managed via three dedicated enable pins (EN_BCK1/2/3), each with a 6 mA internal pull-up current source and 1.2 V Schmitt-trigger threshold. Startup delay is programmable via external capacitors (0.2 ms/nF), enabling custom rail ordering. Overcurrent protection operates in hiccup mode with cycle-by-cycle limiting and thermal shutdown at 160°C.

Key Specifications

Parameter	Value and Actual Design Meaning
Input Voltage Range	10.8 V – 22 V for BUCK1; 4.75 V – 6.1 V for BUCK2/BUCK3 - supports wide-input industrial DC supplies and regulated intermediate rails.
Output Voltage Ranges	BUCK1: 3.3 V – 6.1 V; BUCK2/BUCK3: 0.9 V – 3.3 V - enables core logic, I/O, and memory rails in broadband infrastructure.
Max Output Current	6 A (BUCK1, external FETs); 3 A per channel (BUCK2 & BUCK3, integrated FETs) - sufficient for SoC core and peripheral power domains.
Switching Frequency	500 kHz (BUCK1); 1 MHz (BUCK2 & BUCK3) - balances efficiency vs. size: lower frequency for high-current BUCK1, higher for compact BUCK2/3 designs.
Protection Features	Overcurrent (hiccup mode), thermal shutdown (160°C trip), UVLO (VIN < 4.7 V disables all rails), soft-start (0.4 ms/nF) - ensures robust startup and fault recovery in unattended equipment.
Package & Thermal	40-pin QFN (6 mm × 6 mm, RHA), θ_JA = 18.1°C/W - thermally enhanced for high-power density in space-constrained STB and gateway PCBs.

Pinout & Package

TPS65232A0RHAR is housed in a 40-pin QFN package (RHA) with exposed thermal pad. Pin functions are defined per TI SLVSA42 datasheet Section 5 (TERMINAL FUNCTIONS (RHA)). All analog/digital/power grounds are segregated for noise isolation; bootstrap (BST1/BST2/BST3), switching (PH1/PH2/PH3), and feedback (FB1/FB2/FB3) pins support standard synchronous buck layout practices.

Pin/Terminal	Circuit Role	Design Meaning
VIN	Main input supply for BUCK1 and internal circuitry	Accepts 10.8–22 V; connects to bulk input capacitor and feeds internal 3.3 V/6 V regulators.
EN_BCK1/2/3	Active-high enable inputs	Each has 6 mA internal pull-up; threshold = 1.2 V; capacitor-to-ground sets sequencing delay (0.2 ms/nF).
FB1/FB2/FB3	Feedback inputs for output voltage regulation	Reference voltage = 0.804 V ±2%; external resistor dividers set output (e.g., R11/R12 for BUCK1).
BST1/BST2/BST3	Bootstrap supply inputs for high-side gate drivers	Require 22 nF–100 nF ceramic capacitors between BSTx and PHx to sustain high-side FET drive during 100% duty cycle.
PH1/PH2/PH3	Switch node outputs	Connect to inductor; PH1 drives external FETs; PH2/PH3 drive integrated FETs; require low-ESR ceramic output caps.
TRIP	Current-limit threshold setting	Resistor from TRIP to GND sets BUCK1 overcurrent trip: I_LIM ≈ 10 mA × R_TRIP × 10 / (0.75 × R_DS(ON)) - enables precise OCP tuning.

Key Features

Feature	Design Value
Independent enable-controlled sequencing	Three dedicated EN pins with 6 mA pull-up and programmable RC delay enable deterministic power-up order without external logic.
Integrated FETs for BUCK2/BUCK3	Eliminates 4 external MOSFETs and associated gate-drive components, reducing BOM count and layout area for auxiliary rails.
Type III compensation with internal poles/zeros	Zero at 45 kHz and pole at 240 kHz allow stable operation with ceramic output capacitors and minimal external compensation parts.
Hiccup-mode overcurrent protection	Shuts down affected rail on overload, retries after fixed interval - prevents thermal runaway while maintaining system-level fault tolerance.
Dedicated TRIP pin for BUCK1 current limit	Enables accurate, temperature-compensated OCP (ITRIP = 10 mA ±30%, 3700 ppm/°C) using single external resistor.

Applications

xDSL Modem Power System	Wireless Access Point Baseband
Use Scenario: Powers ADSL2+ chipset (DSP, PHY, analog front-end) requiring tightly sequenced 1.2 V, 1.8 V, and 3.3 V rails from 12 V DC input. IC Role / Device Role / Timing Role: Central PMIC managing all DC-DC conversion, soft-start ramp control, and inter-rail enable timing via EN_BCKx pins. Use Value: Reduces component count by integrating two 3 A buck regulators and one 6 A controller, while enabling compliant power-up per ITU-T G.992.5 timing requirements.	Use Scenario: Supplies dual-band Wi-Fi SoC (2.4 GHz + 5 GHz radios, MAC, memory interface) with independent 1.1 V core, 1.8 V I/O, and 3.3 V RF bias rails. IC Role / Device Role / Timing Role: Multi-rail power manager delivering isolated, sequenced outputs with hiccup-mode fault response to prevent radio lockup during antenna load transients. Use Value: Achieves >95% efficiency at 2 A on 3.3 V rail and maintains <1% load regulation across 0–3 A, ensuring stable RF performance under dynamic traffic.
Set-Top Box Main Board	Home Gateway Router
Use Scenario: Generates 1.2 V CPU core, 1.8 V DDR3, and 3.3 V USB/PCIe interface rails from 12 V wall adapter in cost-sensitive consumer enclosure. IC Role / Device Role / Timing Role: Integrated power solution replacing discrete controllers and regulators, with thermal shutdown protecting against poor ventilation. Use Value: 6 mm × 6 mm QFN footprint saves >40% board area versus discrete alternatives; 18.1°C/W θ_JA sustains full load at 50°C ambient without heatsink.	Use Scenario: Powers ARM-based gateway SoC, Gigabit Ethernet PHY, and multiple USB peripherals from 12 V input in compact fanless housing. IC Role / Device Role / Timing Role: Single-chip PMIC providing three regulated outputs with independent enable control and UVLO coordination across input domains. Use Value: Simultaneous BUCK2/BUCK3 operation at 1 MHz allows smaller inductors (2.2 µH) and 10 µF ceramic caps, cutting solution size by 35% vs. 500 kHz designs.

xDSL Modem Power System

Wireless Access Point Baseband

Use Scenario: Powers ADSL2+ chipset (DSP, PHY, analog front-end) requiring tightly sequenced 1.2 V, 1.8 V, and 3.3 V rails from 12 V DC input.

IC Role / Device Role / Timing Role: Central PMIC managing all DC-DC conversion, soft-start ramp control, and inter-rail enable timing via EN_BCKx pins.

Use Value: Reduces component count by integrating two 3 A buck regulators and one 6 A controller, while enabling compliant power-up per ITU-T G.992.5 timing requirements.

Use Scenario: Supplies dual-band Wi-Fi SoC (2.4 GHz + 5 GHz radios, MAC, memory interface) with independent 1.1 V core, 1.8 V I/O, and 3.3 V RF bias rails.

IC Role / Device Role / Timing Role: Multi-rail power manager delivering isolated, sequenced outputs with hiccup-mode fault response to prevent radio lockup during antenna load transients.

Use Value: Achieves >95% efficiency at 2 A on 3.3 V rail and maintains <1% load regulation across 0–3 A, ensuring stable RF performance under dynamic traffic.

Set-Top Box Main Board

Home Gateway Router

Use Scenario: Generates 1.2 V CPU core, 1.8 V DDR3, and 3.3 V USB/PCIe interface rails from 12 V wall adapter in cost-sensitive consumer enclosure.

IC Role / Device Role / Timing Role: Integrated power solution replacing discrete controllers and regulators, with thermal shutdown protecting against poor ventilation.

Use Value: 6 mm × 6 mm QFN footprint saves >40% board area versus discrete alternatives; 18.1°C/W θ_JA sustains full load at 50°C ambient without heatsink.

Use Scenario: Powers ARM-based gateway SoC, Gigabit Ethernet PHY, and multiple USB peripherals from 12 V input in compact fanless housing.

IC Role / Device Role / Timing Role: Single-chip PMIC providing three regulated outputs with independent enable control and UVLO coordination across input domains.

Use Value: Simultaneous BUCK2/BUCK3 operation at 1 MHz allows smaller inductors (2.2 µH) and 10 µF ceramic caps, cutting solution size by 35% vs. 500 kHz designs.

Equivalent & Alternatives

The following parts are listed as comparable options for similar multi-output buck regulator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
TPS65233A0RGER	Same pinout, identical BUCK2/BUCK3 architecture, but BUCK1 is a 6-A integrated buck (not controller); no external FET support.	Suitable where full integration is preferred and 6-A BUCK1 current is sufficient without external FET flexibility.	Select TPS65233A0RGER if external high-current FETs are unnecessary and board space is critical.
TPS65217CRSLR	4-channel PMIC with LDOs, battery charger, and fuel gauge; BUCKs limited to 3 A max; different pinout and sequencing logic.	Targets portable/battery-powered devices; lacks BUCK1 controller capability and wide 10.8–22 V input range.	Choose TPS65217CRSLR only for battery-backed systems requiring integrated charging and fuel gauging - not for mains-powered broadband gear.

Compared with TPS65232A0RHAR, TPS65233A0RGER trades BUCK1 controller flexibility for smaller solution size and simpler layout, while TPS65217CRSLR shifts focus to portable power management with incompatible input range and sequencing architecture.

Availability

TPS65232A0RHAR is available at Aetrix Electronics and suitable for xDSL modems, wireless access points, and home gateways requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.

Supply support for TPS65232A0RHAR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management solutions, with decades of expertise in high-reliability power IC design for communications infrastructure.

The TPS65232 product line delivers highly integrated, thermally optimized multi-rail PMICs for broadband customer premises equipment, emphasizing sequencing control, efficiency, and protection in space-constrained 12 V–22 V input systems.

FAQ

What is the function of the TRIP pin on the TPS65232A0RHAR?

The TRIP pin on the TPS65232A0RHAR sets the overcurrent threshold for BUCK1 using an external resistor. A 10 mA internal current source flows through the resistor to ground, generating a reference voltage that compares against the low-side MOSFET's R_DS(ON) voltage drop. This enables precise, temperature-compensated current limiting (3700 ppm/°C) without additional sensing circuitry. The TPS65232A0RHAR uses this signal to initiate hiccup-mode shutdown when the calculated inductor current exceeds the programmed limit.

Can the TPS65232A0RHAR support custom power-up sequencing between its three buck outputs?

Yes, the TPS65232A0RHAR supports fully customizable power-up sequencing via its three independent enable pins (EN_BCK1, EN_BCK2, EN_BCK3). Each pin features a 6 mA internal pull-up current source and a 1.2 V Schmitt-trigger comparator. By connecting a capacitor from any EN pin to ground, a controlled voltage ramp is generated (0.2 ms delay per 1 nF), allowing precise staggered activation. The TPS65232A0RHAR defaults to BUCK1→BUCK2→BUCK3 if all enables are tied high, but custom delays exceeding 2.5 ms ensure deterministic ordering per application requirements.

What package type and thermal characteristics does the TPS65232A0RHAR use?

The TPS65232A0RHAR uses a 40-pin QFN package (6 mm × 6 mm, RHA) with an exposed thermal pad. Its junction-to-ambient thermal resistance (θ_JA) is 18.1°C/W on a JEDEC High-K 4-layer board, enabling 2.5 W maximum continuous power dissipation at 75°C ambient. The package supports efficient heat transfer to the PCB via the thermal pad, and the TPS65232A0RHAR incorporates thermal shutdown at 160°C with 20°C hysteresis to protect against sustained overload conditions.

How does the TPS65232A0RHAR handle overcurrent events on BUCK2 and BUCK3?

The TPS65232A0RHAR handles overcurrent events on BUCK2 and BUCK3 using hiccup-mode protection. When excessive current is detected via internal MOSFET R_DS(ON) sensing, the affected regulator shuts down for a fixed recovery period before attempting restart. If the overload persists, the cycle repeats - preventing thermal runaway while maintaining system awareness. Unlike latch-off schemes, this behavior allows automatic recovery upon fault removal, and the TPS65232A0RHAR coordinates all three rails' enable states during UVLO or thermal events to preserve safe sequencing.

What are the key differences between the TPS65232A0RHAR and the TPS65232A2DCAR?

The TPS65232A0RHAR and TPS65232A2DCAR share identical electrical specifications and functional blocks but differ in package and pinout. The TPS65232A0RHAR uses a 40-pin QFN (RHA), while the TPS65232A2DCAR uses a 48-pin HTSSOP (DCA). Their pin assignments, thermal performance (θ_JA = 18.1°C/W vs. 25°C/W), and PCB layout requirements are incompatible. The TPS65232A0RHAR offers superior power density and thermal efficiency, making it preferred for space-constrained, high-power applications where the QFN footprint is acceptable.

TPS65232A0RHAR Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: -

Package/Case:: 40-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Applications:: Controller/Converter, Satellite Boxes, xDSL and Cable Modems

Voltage - Input:: 4.75V ~ 22V

Number of Outputs:: 3

Voltage - Output:: 0.9V ~ 3.3V, 3.3V ~ 6.1V

Operating Temperature:: 0°C ~ 85°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 40-VQFN (6x6)

TPS65232A0RHAR FAQ

1.How can I place an order for TPS65232A0RHAR through Aetrix?

Please submit a Request for Quotation (RFQ) for TPS65232A0RHAR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for TPS65232A0RHAR reliable?

The price and inventory of TPS65232A0RHAR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS65232A0RHAR is usually 5 days.

3.What payment methods are accepted for TPS65232A0RHAR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS65232A0RHAR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for TPS65232A0RHAR?

TPS65232A0RHAR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your TPS65232A0RHAR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for TPS65232A0RHAR?

For technical support, including TPS65232A0RHAR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS65232A0RHAR requirements.

6.How does Aetrix verify that TPS65232A0RHAR is sourced from the original manufacturer or authorized distributors?

All TPS65232A0RHAR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS65232A0RHAR meets industry standards.

7.What is the process for return or replacement of TPS65232A0RHAR?

All TPS65232A0RHAR units undergo pre-shipment inspection (PSI). If there is an issue with TPS65232A0RHAR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The TPS65232A0RHAR part is unused and in its original packaging.

Return procedure for TPS65232A0RHAR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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