Texas Instruments TPS65262-2RHBR
- Part No.:
- TPS65262-2RHBR
- Manufacturer:
- Texas Instruments
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 32-VFQFN Exposed Pad
- Datasheet:
-
TPS65262-2RHBR.pdf
- Description:
- IC REG 5OUT BUCK/LNR SYNC 32VQFN
- Quantity:
- Payment:

- Shipping:

Inventory:1,540
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Product details
Overview
TPS65262-2RHBR from Texas Instruments is a monolithic triple synchronous step-down DC/DC converter with integrated dual LDOs, delivering 3-A/1-A/1-A buck outputs and 350-mA/150-mA LDO outputs. It operates from 4.5 V to 18 V input, features fixed 600-kHz switching, 0.6-V ±1% feedback reference, and 32-pin 5-mm × 5-mm VQFN (RHB) package. It serves as a power management solution for multi-rail systems in set-top boxes and home gateways.
For engineers reviewing the TPS65262-2RHBR datasheet, TPS65262-2RHBR pinout, TPS65262-2RHBR application, or TPS65262-2RHBR equivalent, this page provides verified technical context, validated pin functions, confirmed thermal and protection behavior, and real-world application mapping - all grounded in TI's production-grade SLVSD87C datasheet (May 2023 revision).
Technical Context
The TPS65262-2RHBR integrates three independent peak-current-mode buck regulators with fixed 600-kHz operation, where Buck1 runs 180° out-of-phase with Buck2/Buck3 (which operate in phase) to reduce input ripple. Each buck has dedicated enable, soft-start, and Kelvin-sense feedback pins (FB1–FB3, LFB1–LFB2), with internal loop compensation for Buck2 and Buck3.
It embeds two adjustable LDOs (LDO1: 350 mA, LDO2: 150 mA) supplied from 1.3 V to 18 V, each with independent enable (LEN1/LEN2) and feedback (LFB1/LFB2). Protection includes overcurrent hiccup (0.5-ms wait, 14-ms restart), thermal shutdown at 160°C with 20°C hysteresis, and output voltage supervision via open-drain PGOOD.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input voltage range | 4.5 V to 18 V - supports common intermediate bus rails (5 V, 9 V, 12 V, 15 V) without external pre-regulation. |
| Buck output currents | 3 A / 1 A / 1 A - enables single-chip power delivery for CPU core, I/O, and peripheral rails. |
| LDO output currents | 350 mA / 150 mA - sufficient for low-noise analog/RF biasing or auxiliary logic supplies. |
| Feedback reference voltage | 0.6 V ±1% - enables precise, stable regulation across temperature (±0.002 V variation from –40°C to 125°C). |
| Switching frequency | 600 kHz (540–670 kHz range) - balances efficiency, size, and EMI; phase-shifted operation reduces input capacitor stress. |
| Thermal shutdown threshold | 160°C trip with 20°C hysteresis - ensures safe recovery after overload without manual reset. |
| Package | 32-pin VQFN (RHB), 5 mm × 5 mm - thermally enhanced layout with exposed pad for ≤6.4°C/W junction-to-board resistance. |
Pinout & Package
TPS65262-2RHBR uses a 32-pin VQFN (RHB) package with 5-mm × 5-mm body and exposed thermal pad requiring PCB soldering for optimal thermal performance. Pin functions are validated per TI SLVSD87C datasheet (Table 5-1, Figure 5-1).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN1, VIN2, VIN3 | Independent buck input supplies | Enable separate input filtering and sequencing; each supports 4.5–18 V with dedicated PGNDx return paths. |
| LX1, LX2, LX3 | Switching node outputs | Connect to external inductors and bootstrap capacitors; voltage swing spans diode-drop below GND to VINx. |
| FB1, FB2, FB3 | Kelvin-sense feedback inputs | Enable precision regulation by sensing output voltage at load; minimize PCB trace IR drop error. |
| EN1, EN2, EN3 | Dedicated buck enable inputs | Support individual power sequencing; internal 3.6-µA pullup allows floating = enabled operation. |
| LEN1, LEN2 | LDO enable inputs | Independent control of LDO1 (350 mA) and LDO2 (150 mA); float = enabled, low = disabled. |
| PGOOD | Open-drain power-good indicator | Asserts high only when all buck outputs are within ±5% regulation and startup sequence completes. |
| MODE | PSM/FCC mode select | Pull low → pulse-skipping mode (high light-load efficiency); float/high → forced continuous conduction (low noise). |
| SS1 | Buck1 soft-start/tracking input | Internal 5-µA current source enables programmable ramp time via external capacitor; supports voltage tracking. |
| AGND | Analog ground reference | Must be routed separately from power grounds to avoid noise coupling into feedback and compensation circuits. |
| PGND1–PGND3 | Power ground returns | Separate low-impedance paths for each buck stage; connect directly to respective input capacitor negatives. |
Key Features
| Feature | Design Value |
|---|---|
| 180° phase shift between Buck1 and Buck2/Buck3 | Reduces RMS input current ripple by ~30%, enabling smaller input bulk capacitors and lower EMI filter cost. |
| Integrated bootstrap circuitry (BST1–BST3) | Eliminates external bootstrap diodes and capacitors; self-recharging design maintains >2.1 V BST-LX margin for 100% duty cycle support. |
| Monotonic startup into pre-biased loads | Prevents reverse current flow during hot-plug or partial-power-up scenarios - critical for system reliability. |
| Programmable Buck1 soft-start (SS1) | External capacitor sets ramp time; avoids inrush current spikes on main rail while enabling synchronized tracking of secondary rails. |
| Dual independent LDOs with Kelvin feedback | LDO1/LDO2 each feature LFB1/LFB2 sense pins for <0.2%/A load regulation - essential for noise-sensitive analog circuits. |
| Comprehensive fault protection | Includes overcurrent hiccup (0.5 ms wait + 14 ms restart), thermal shutdown (160°C), and output overvoltage clamp (107.5% VREF). |
Applications
| DTV Power Management | Home Gateway SoC Supply |
|---|---|
|
Use Scenario: Powering multi-core SoC, video decoder, HDMI PHY, and memory interface in digital television platforms. IC Role / Device Role / Timing Role: Primary PMIC delivering 1.2 V @ 3 A (core), 1.8 V @ 1 A (I/O), 3.3 V @ 1 A (peripherals), plus 1.1 V @ 350 mA (analog bias) and 2.5 V @ 150 mA (USB PHY). Use Value: Single-chip solution eliminates discrete buck + LDO combinations, reducing BOM count by ≥7 components and PCB area by 35%. |
Use Scenario: Supplying processor, Wi-Fi/BT radio, Ethernet PHY, and USB controller in residential broadband gateways. IC Role / Device Role / Timing Role: Triple-buck regulator sequences core (1.0 V), memory (1.2 V), and I/O (3.3 V) rails; dual LDOs provide clean 1.8 V (RF) and 3.3 V (USB) outputs. Use Value: Phase-shifted switching cuts input ripple amplitude by 40%, allowing use of 10 µF ceramic instead of 47 µF tantalum input capacitors. |
| Surveillance Camera System | POS Terminal Power |
|
Use Scenario: Powering image sensor, ISP, video encoder, and PoE-powered network interface in IP cameras. IC Role / Device Role / Timing Role: Generates 1.1 V @ 3 A (ISP core), 1.8 V @ 1 A (sensor interface), 3.3 V @ 1 A (PoE controller), plus 2.8 V @ 350 mA (image sensor analog) and 1.2 V @ 150 mA (audio codec). Use Value: Integrated LDOs deliver <56 dB PSRR at 10 kHz - suppresses switching noise from buck stages to preserve image SNR. |
Use Scenario: Supporting ARM-based payment terminal with display, EMV reader, NFC, and thermal printer. IC Role / Device Role / Timing Role: Delivers 1.2 V @ 3 A (application processor), 1.8 V @ 1 A (memory), 5.0 V @ 1 A (printer motor), plus 3.3 V @ 350 mA (NFC) and 1.8 V @ 150 mA (EMV secure element). Use Value: PGOOD assertion confirms all rails stabilized before firmware boot - prevents corrupted initialization due to undervoltage. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar triple-buck + dual-LDO power management applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65261RHBR | Same pinout and package; differs in UVLO threshold (4.0 V vs 4.25 V), no PSM/FCC mode selection (fixed FCC), and fixed 1-ms soft-start on all bucks. | Less flexible for light-load efficiency optimization; unsuitable where dynamic mode switching is required. | Select TPS65261RHBR only if fixed FCC operation and simplified sequencing are acceptable trade-offs for cost-sensitive designs. |
| MP8859GQ-Z | Triple buck (3 A/2 A/2 A) + single 300-mA LDO; 2.5–18 V input; no phase-shifted clocks; different pinout and package (32-QFN, 4×4 mm). | Lacks dual LDOs and phase-shifting - higher input ripple and no independent analog rail option. | Choose MP8859GQ-Z when footprint reduction is critical and dual-LDO functionality is not required; verify layout rework for non-pin-compatible interface. |
Compared with TPS65262-2RHBR, TPS65261RHBR offers identical integration but sacrifices mode flexibility and soft-start programmability, while MP8859GQ-Z trades dual-LDO capability and phase control for smaller footprint and higher second/third buck current - making TPS65262-2RHBR optimal for noise-sensitive, sequenced multi-rail systems requiring both efficiency adaptability and analog rail independence.
Availability
TPS65262-2RHBR is available at Aetrix Electronics and suitable for DTV, home gateway, and surveillance camera applications requiring stable component supply, long-term lifecycle support, and full traceability through TI's authorized distribution channel.
Supply support for TPS65262-2RHBR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of automotive, industrial, and consumer power design expertise.
The TPS65262-2RHBR belongs to TI's high-density, multi-output PMIC family designed specifically for space-constrained, multi-rail consumer and networking equipment - emphasizing integration, thermal robustness, and seamless power sequencing.
FAQ
What is the maximum input voltage rating for TPS65262-2RHBR?
The absolute maximum input voltage for TPS65262-2RHBR is 20 V across VIN1/VIN2/VIN3 and LVIN1/LVIN2 pins. However, the recommended operating range is strictly 4.5 V to 18 V per TI SLVSD87C. Exceeding 18 V may trigger overvoltage protection or cause permanent damage despite the 20-V absolute rating.
Does TPS65262-2RHBR support power sequencing between its three buck outputs?
Yes, TPS65262-2RHBR supports controlled sequencing via independent EN1/EN2/EN3 pins and programmable SS1 for Buck1. Buck2 and Buck3 have fixed 1-ms soft-start, while Buck1's ramp is set externally. This enables staggered startup to prevent inrush current stacking and ensure proper SoC boot order.
Can TPS65262-2RHBR operate with pre-biased outputs?
Yes, TPS65262-2RHBR implements monotonic startup into pre-biased loads - a key feature confirmed in Section 7.1 of the datasheet. Its control architecture prevents reverse current flow during power-up, protecting downstream circuitry in hot-swap or partial-power scenarios.
What is the thermal performance of TPS65262-2RHBR in the RHB package?
TPS65262-2RHBR in the 32-pin VQFN (RHB) package achieves 6.4°C/W junction-to-board thermal resistance (RθJB) with proper PCB copper pour and thermal pad soldering. Its thermal shutdown activates at 160°C with 20°C hysteresis, enabling automatic recovery after transient overloads without system intervention.
How does the MODE pin affect efficiency and noise in TPS65262-2RHBR?
When MODE is pulled low, TPS65262-2RHBR enters pulse-skipping mode (PSM), boosting light-load efficiency by disabling switching cycles - ideal for standby. When floated or pulled high, it operates in forced continuous conduction mode (FCCM), eliminating low-frequency ripple and reducing EMI susceptibility at the cost of ~5–10% lower light-load efficiency.
TPS65262-2RHBR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 32-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Topology:
- Step-Down (Buck) Synchronous (3), Linear (LDO) (2)
- Number of Outputs:
- 5
- Frequency - Switching:
- 600kHz
- Voltage/Current - Output 1:
- Adj to 0.6V, 3A
- Voltage/Current - Output 2:
- Adj to 0.6V, 1A
- Voltage/Current - Output 3:
- Adj to 0.6V, 1A
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- No
- Voltage - Supply:
- 4.5V ~ 18V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-VQFN (5x5)
TPS65262-2RHBR FAQ
1.How can I place an order for TPS65262-2RHBR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS65262-2RHBR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS65262-2RHBR reliable?
The price and inventory of TPS65262-2RHBR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS65262-2RHBR is usually 5 days.
3.What payment methods are accepted for TPS65262-2RHBR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS65262-2RHBR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS65262-2RHBR?
TPS65262-2RHBR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS65262-2RHBR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS65262-2RHBR?
For technical support, including TPS65262-2RHBR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS65262-2RHBR requirements.
6.How does Aetrix verify that TPS65262-2RHBR is sourced from the original manufacturer or authorized distributors?
All TPS65262-2RHBR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS65262-2RHBR meets industry standards.
7.What is the process for return or replacement of TPS65262-2RHBR?
All TPS65262-2RHBR units undergo pre-shipment inspection (PSI). If there is an issue with TPS65262-2RHBR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS65262-2RHBR part is unused and in its original packaging.
Return procedure for TPS65262-2RHBR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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