Texas Instruments TPS65680RSNR

Overview

TPS65680RSNR from Texas Instruments is a programmable 18-channel LCD panel level shifter IC for GIP/GOA-based displays, delivering 12 high-voltage clock outputs (GCK1–GCK12), 6 high-voltage control outputs (GSP1/GSP2, GCP, GGP1/GGP2, VSS), and integrated overcurrent protection. It operates with VIN = 2.8–5.5 V, VGH = 9–40 V, and VGL1/VGL2 = –4 to –18 V, and supports pattern-programmable timing sequences for TV, monitor, and industrial LCD panels.

For engineers reviewing the TPS65680RSNR datasheet, TPS65680RSNR pinout, TPS65680RSNR application, or TPS65680RSNR equivalent, key selection considerations include its 32-pin WQFN package, I²C-configurable OCP thresholds (20–320 mA), gate-voltage shaping capability, panel discharge sequencing, and dual-VGL support for bipolar LCD biasing.

Technical Context

The TPS65680RSNR implements a user-defined pattern sequencer driven by LN_CLK and LS_START inputs from the timing controller, eliminating need for external frame-synchronized clocks. Its digital core uses an internal 2-MHz oscillator or PLL-synchronized operation (3–15 MHz) with <450 ppm lock accuracy and 8-ms lock time at 40 kHz input.

It integrates independent overcurrent sensing per supply rail (VGH, VGL1, VGL2), with programmable alarm counters (ALARM1 for clock channels, ALARM2 for control channels) and fault recovery requiring full power cycle. Power-good supervision validates all three bias rails before enabling outputs, and panel discharge executes in two configurable steps triggered by LS_CNTRL falling edge.

Key Specifications

Pinout & Package

The TPS65680RSNR is housed in a 4.0 mm × 4.0 mm, 32-pin WQFN package (RSN) with thermal pad connected to VGL2. Pin functions are validated per TI SLVSE46A datasheet Rev A (January 2018).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LCD panel level shifter applications.

Compared with TPS65680RSNR, TPS65682RSNR adds analog VCOM support but increases system complexity, while BD8153FVJ-E2 reduces channel count and eliminates programmability-making TPS65680RSNR optimal for mid-to-large GOA panels needing field-tunable timing and robust dual-rail discharge.

Availability

TPS65680RSNR is available at Aetrix Electronics and suitable for TV display modules, industrial HMI systems, and notebook LCD biasing requiring stable component supply, long-lifecycle availability, and automotive-grade reliability screening.

Supply support for TPS65680RSNR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of experience in display interface and bias solutions.

The TPS65680RSNR belongs to TI's LCD panel power and timing IC product line, engineered specifically for GOA/GIP architectures to replace discrete level-shifting and sequencing circuits in large-format, high-resolution displays.

FAQ

What is the primary function of the TPS65680RSNR in an LCD system?

The TPS65680RSNR serves as a programmable high-voltage level shifter that generates all timing signals for GOA/GIP LCD panels-including 12 clock outputs (GCK1–GCK12), 6 control outputs (GSP1/GSP2, GCP, GGP1/GGP2, VSS), and panel discharge sequencing. It replaces multiple discrete level shifters and simplifies timing controller (TCON) interface with only two required signals: LN_CLK and LS_START. The TPS65680RSNR enables flexible, software-defined panel driving without hardware changes.

How does the TPS65680RSNR handle overcurrent protection?

The TPS65680RSNR implements per-rail overcurrent protection (OCP) on VGH, VGL1, and VGL2 supplies, with thresholds adjustable from 20 mA to 320 mA in 20-mA steps via I²C registers. It maintains separate alarm counters (ALARM1 for clock channels, ALARM2 for control channels); exceeding the programmed event limit forces all outputs into HiZ and enters FAULT mode. Recovery requires a full power cycle-no automatic reset. This behavior is documented in the TPS65680RSNR datasheet Section 7.3.5 and electrical characteristics Table 6.5.

Can the TPS65680RSNR support dual-negative bias supplies (VGL1 and VGL2)?

Yes, the TPS65680RSNR explicitly supports independent VGL1 and VGL2 supplies ranging from –4 V to –18 V each. VGL1 powers GCK7/GCK8 outputs, while VGL2 connects to the thermal pad and supplies GCK1–GCK6, GCK9–GCK12, GSP1/GSP2, GCP, GGP1/GGP2, and VSS. If only one negative supply is available, VGL1 and VGL2 must be shorted together per datasheet Section 7.3.1. The thermal pad must be connected to the most negative supply-either dedicated VGL2 or VGL1 if shared.

What is the role of the CS1 and CS2 pins on the TPS65680RSNR?

CS1 and CS2 are charge-sharing and gate-voltage shaping terminals on the TPS65680RSNR. CS1 connects to GCK1–GCK6 outputs to shape their waveforms and reduce ringing; CS2 connects to GCK7–GCK12 for the same purpose. These pins allow external RC networks to fine-tune rise/fall times and overshoot, improving EMI performance and gate driver efficiency in high-resolution LCD panels. Their use is optional-pins may be left floating if not needed-and is detailed in the TPS65680RSNR pin function table (Section 5) and feature description (Section 7.3.7).

Does the TPS65680RSNR require external programming during normal operation?

No-the TPS65680RSNR stores default configuration and pattern data in on-chip nonvolatile memory (NVM), allowing it to boot and operate autonomously after power-up without external programming. I²C writes are optional and used only for dynamic updates (e.g., panel tuning, firmware patches). NVM supports up to 9 write cycles with 10-year data retention at TJ ≤85°C. The TPS65680RSNR datasheet specifies boot time as 1.5 ms from VIN crossing UVLO to readiness for I²C communication, confirming self-contained startup behavior.