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Texas Instruments TPS70145PWP
- Part No.:
- TPS70145PWP
- Manufacturer:
- Texas Instruments
- Package:
- 20-PowerTSSOP (0.173", 4.40mm Width)
- Datasheet:
-
TPS70145PWP.pdf
- Description:
- IC REG LINEAR 3.3V/1.2V 20HTSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:245
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Product details
Overview
TPS70145PWP from Texas Instruments is a dual-output low-dropout voltage regulator with programmable power-up sequencing, delivering fixed 3.3V/1.2V outputs, 500mA on Regulator 1 and 250mA on Regulator 2, ±2% output accuracy over load and temperature, and ultra-low 190µA typical quiescent current - designed for split-voltage DSP systems requiring precise sequencing and low-noise supply.
For engineers reviewing the TPS70145PWP datasheet, TPS70145PWP pinout, TPS70145PWP application, or TPS70145PWP equivalent, this page provides verified technical context, validated pin functions, confirmed sequencing behavior (SEQ-controlled VOUT2-first or VOUT1-first startup), real-world noise performance (65mVRMS without bypass capacitor), and accurate alternative part comparisons for TMS320 DSP, FPGA, and ASIC power management designs.
Technical Context
The TPS70145PWP integrates two independent PMOS-based LDO regulators with separate input pins (VIN1/VIN2), enabling flexible sourcing of 3.3V and 1.2V rails. Its SEQ pin controls power-up order via internal 6µA pull-up, allowing VOUT2-first (SEQ open/high) or VOUT1-first (SEQ low) sequencing with 83% threshold detection and automatic VOUT1 disable if VOUT2 drops below regulation.
It features integrated SVS monitoring: RESET (open-drain, 120ms delay, tracks VOUT2 + MR1/MR2) and PG1 (open-drain, tracks VOUT1 at 95% threshold), both with 30ms rising-edge deglitching and 0.15V output low voltage at 1mA load. Undervoltage lockout activates below VIN1 = 2.4V, and thermal shutdown triggers at TJ = +150°C.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltages | Fixed 3.3V (Regulator 1) and 1.2V (Regulator 2); no external feedback required for nominal operation. |
| Output Current Capability | 500mA max on VOUT1, 250mA max on VOUT2 - supports core+I/O rail delivery for TMS320C5x/C6x DSPs. |
| Quiescent Current | 190µA typical (both regulators enabled); drops to 1mA in standby (EN high) - enables battery-backed or low-power sleep modes. |
| Dropout Voltage | 170mV typical at 500mA (VOUT1), enabling operation with VIN1 as low as 3.47V for 3.3V output. |
| Output Noise | 65mVRMS (300Hz–50kHz, no bypass cap) - eliminates need for external noise-filtering capacitors in sensitive analog/digital mixed-signal paths. |
| Power-On Reset | Open-drain RESET with 120ms delay after VOUT2 reaches 95%; monitors VOUT2, MR1, and MR2 simultaneously. |
| Accuracy | ±2% over full load (0–500mA Reg1 / 0–250mA Reg2) and temperature (–40°C to +125°C) - ensures reliable logic-level compliance. |
Pinout & Package
TPS70145PWP uses a 20-pin HTSSOP package with PowerPAD™ thermal enhancement (PWP designation), measuring 6.5mm × 4.4mm × 1.2mm, with exposed thermal pad soldered to PCB ground plane for improved thermal dissipation (θJB = 19.7°C/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| EN (Pin 6) | Active-low enable input | Puts both regulators into 1mA standby when pulled high; enables sequencing when pulled low. |
| SEQ (Pin 7) | Sequencing control input | Internal 6µA pull-up; VOUT2-first if floating/high, VOUT1-first if pulled low - no external components needed. |
| VIN1 (Pins 2,3) | Regulator 1 input supply | Primary bias source; powers internal circuitry and Regulator 1 (3.3V output); UVLO threshold = 2.4V–2.65V. |
| VIN2 (Pins 9,10) | Regulator 2 input supply | Independent input for Regulator 2 (1.2V output); allows different source domains (e.g., buck converter vs. linear pre-regulator). |
| VOUT1 (Pins 18,19) | Regulator 1 output | Dual-pin configuration reduces IR drop and improves current sharing; delivers up to 500mA at 3.3V ±2%. |
| VOUT2 (Pins 12,13) | Regulator 2 output | Dual-pin configuration; supplies up to 250mA at 1.2V ±2% for DSP core or low-voltage FPGA banks. |
| PG1 (Pin 16) | Power-good indicator for VOUT1 | Open-drain output goes high-Z when VOUT1 ≥95% of 3.3V; requires external pull-up for system monitoring. |
| RESET (Pin 15) | System reset signal | Open-drain output asserts low if VOUT2 <95%, MR1 low, or MR2 low; 120ms delay prevents false resets during startup. |
| MR1/MR2 (Pins 4,5) | Manual reset inputs | Active-low, internally pulled up to VIN1 with 6µA current; allow external pushbutton or supervisor IC to trigger system reset. |
| VSENSE1/FB1 (Pin 17) | VOUT1 sense / FB for adjustable mode | For fixed 3.3V mode: connect directly to VOUT1; for adjustable mode: connect to resistor divider (not used in TPS70145). |
| VSENSE2/FB2 (Pin 14) | VOUT2 sense / FB for adjustable mode | For fixed 1.2V mode: connect directly to VOUT2; for adjustable mode: connect to resistor divider (not used in TPS70145). |
| GND (Pin 8) | Analog/digital ground reference | Single ground pin shared by both regulators; must be connected to low-impedance PCB ground plane. |
Key Features
| Feature | Design Value |
|---|---|
| Programmable Power-Up Sequencing | SEQ pin selects VOUT2-first (default) or VOUT1-first startup with automatic interlock - eliminates external timing RC networks. |
| Ultra-Low Quiescent Current | 190µA typical across full load range (0–500mA), enabling >1-year battery life in always-on supervisory applications. |
| Integrated SVS Monitoring | Separate PG1 (VOUT1) and RESET (VOUT2 + MR1/MR2) outputs with 120ms delay and 30ms deglitching - replaces discrete reset ICs. |
| Low-Noise Operation Without Bypass Caps | 65mVRMS output noise (300Hz–50kHz) achieved via internal compensation - saves board space and BOM cost. |
| Thermal Protection with PowerPAD™ | Exposed thermal pad lowers θJB to 19.7°C/W; thermal shutdown at +150°C prevents damage during overload or poor airflow. |
Applications
| TMS320 DSP Core + I/O Supply | FPGA Dual-Rail Power Management |
|---|---|
|
Use Scenario: Powering TI TMS320C6713 DSP where core requires 1.2V @ 250mA and I/O banks require 3.3V @ 500mA, with strict 83% sequencing margin to prevent latch-up. IC Role / Device Role / Timing Role: Dual-LDO regulator providing sequenced, low-noise, ±2% accurate rails; SEQ pin configures VOUT2 (1.2V core) to power first, then VOUT1 (3.3V I/O) after stabilization. Use Value: Eliminates need for external sequencing IC or discrete MOSFET controllers; reduces component count by 3–5 parts and PCB area by >12mm². |
Use Scenario: Supplying Xilinx Spartan-3 FPGA with 1.2V core and 3.3V bank, requiring independent input sourcing and reset coordination between rails. IC Role / Device Role / Timing Role: Dual-output LDO with independent VIN1/VIN2 inputs and synchronized RESET/PG1 outputs - enables clean power-up and brownout detection per rail. Use Value: PG1 monitors core rail integrity; RESET combines VOUT2 status and manual reset inputs - simplifies system-level fault handling without additional supervisors. |
| ASIC Split-Voltage System | Industrial Embedded Controller |
|
Use Scenario: Powering custom ASIC with 3.3V interface and 1.2V logic core, operating in –40°C to +125°C ambient with minimal thermal margin. IC Role / Device Role / Timing Role: High-accuracy LDO with ±2% regulation over full temp/load, thermal shutdown at +150°C, and PowerPAD™ for enhanced heat transfer. Use Value: Maintains voltage compliance under worst-case conditions; thermal pad reduces junction rise by ~15°C vs. standard TSSOP - extends reliability in sealed enclosures. |
Use Scenario: Compact industrial controller using ARM Cortex-M4 with 3.3V peripherals and 1.2V core, requiring long-term supply continuity and low standby consumption. IC Role / Device Role / Timing Role: Low-quiescent-current dual LDO (190µA typ) with EN-controlled shutdown and 1mA standby mode - enables energy harvesting or supercap backup. Use Value: Reduces system standby power by >40% vs. discrete single-rail LDOs; RESET/PG1 signals feed MCU's WDT and supply monitor peripherals directly. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output LDO regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS70245PWP | Same 3.3V/1.2V outputs and PWP package, but lacks SEQ pin and programmable sequencing - fixed VOUT1-first startup only. | Not suitable for DSP systems requiring VOUT2-first sequencing; acceptable for simpler ASIC/FPGA where sequencing order is non-critical. | Select TPS70245PWP only if sequencing flexibility is unnecessary and BOM cost reduction is prioritized over design adaptability. |
| TPS7A8300RGRT | Single 3.3V output (500mA), 12µA IQ, 35µVRMS noise, 6-pin QFN - no second rail or sequencing capability. | Requires separate 1.2V regulator (e.g., TPS7A16) and external sequencing logic - increases design complexity and footprint. | Choose TPS7A8300RGRT only when highest PSRR (>70dB at 1kHz) and lowest noise are mandatory, and dual-rail integration is secondary. |
Compared with TPS70145PWP, TPS70245PWP sacrifices sequencing control for lower cost and reduced pin count, while TPS7A8300RGRT offers superior noise/PSRR but forces discrete dual-rail implementation - making TPS70145PWP optimal for integrated, sequenced DSP power where board space and reliability are constrained.
Availability
TPS70145PWP is available at Aetrix Electronics and suitable for TMS320 DSP power systems, FPGA dual-rail designs, and industrial embedded controllers requiring stable component supply, guaranteed long-term availability, and traceable sourcing through TI-authorized channels.
Supply support for TPS70145PWP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in high-reliability, high-performance power solutions for industrial, automotive, and communications markets.
The TPS701xx family was designed specifically for split-voltage digital signal processors and ASICs requiring tightly regulated, sequenced dual-rail supplies - emphasizing accuracy, low noise, and integrated supervision without external components.
FAQ
What is the correct power-up sequence behavior of the TPS70145PWP when the SEQ pin is left unconnected?
When the SEQ pin is left unconnected (floating), the internal 6µA pull-up current sources it to VIN1, resulting in VOUT2 (1.2V) powering up first. VOUT1 (3.3V) remains disabled until VOUT2 reaches approximately 83% of its regulated output voltage, at which point VOUT1 turns on. This behavior is confirmed in the SLVS222I datasheet Figure 40 and Table 1 terminal description - no external pull-up resistor is required for default VOUT2-first sequencing in the TPS70145PWP.
Does the TPS70145PWP require external bypass capacitors to meet its 65mVRMS noise specification?
No, the TPS70145PWP achieves 65mVRMS output noise (300Hz–50kHz) without any external bypass capacitors, as explicitly stated in the datasheet Feature list and Electrical Characteristics table. This performance is enabled by internal compensation and PMOS pass transistor architecture. Adding large bypass caps may destabilize the regulator; the recommended output capacitor is 33µF low-ESR ceramic, not a noise-filtering bypass.
How does the RESET output of the TPS70145PWP respond when MR1 is pulled low while VOUT2 is stable?
When MR1 is pulled low (≤0.7V), the RESET output of the TPS70145PWP immediately asserts low (active state), regardless of VOUT2 status - because RESET monitors MR1, MR2, and VOUT2 OR-logically. The 120ms delay applies only to the power-on assertion (high-Z to high-Z transition after valid conditions), not to reset assertion. This behavior is defined in the RESET Terminal section of the Electrical Characteristics table and confirmed in the Detailed Description.
Can the TPS70145PWP operate with VIN2 lower than 2.7V, given its specified minimum input voltage?
No - the TPS70145PWP requires VIN2 ≥2.7V under recommended operating conditions, as specified in the "Recommended Operating Conditions" table. For the 1.2V output, the absolute minimum input is 2.7V or VOUT + 1V (2.2V), whichever is greater; thus 2.7V is enforced. Attempting VIN2 = 2.5V violates specifications and risks dropout, instability, or failure to regulate, as confirmed by the VI(min) equation and thermal derating curves in the datasheet.
What is the function of the VSENSE1/FB1 and VSENSE2/FB2 pins on the TPS70145PWP?
On the TPS70145PWP, VSENSE1/FB1 (Pin 17) and VSENSE2/FB2 (Pin 14) serve as output voltage sense inputs for the fixed-output configuration. They must be connected directly to their respective VOUT1 and VOUT2 pins - not to external dividers - to close the feedback loop. These pins are not used for adjustment (the TPS70145 is fixed 3.3V/1.2V), and connecting them elsewhere will cause regulation failure, as detailed in the "Device Information" and "Pin Functions" sections of the SLVS222I datasheet.
TPS70145PWP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 20-PowerTSSOP (0.173", 4.40mm Width)
- Packaging:
- Bulk
- Product Status:
- Active
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 2
- Voltage - Input (Max):
- 6V
- Voltage - Output (Min/Fixed):
- 3.3V, 1.2V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.28V @ 500mA, -
- Current - Output:
- 500mA, 250mA
- Current - Quiescent (Iq):
- 190 µA
- Current - Supply (Max):
- 230 µA
- PSRR:
- 60dB (1kHz)
- Control Features:
- Enable, Power Good, Reset, Sequencing
- Protection Features:
- Over Current, Over Temperature, Reverse Polarity, Under Voltage Lockout (UVLO)
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-HTSSOP
TPS70145PWP FAQ
1.How can I place an order for TPS70145PWP through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS70145PWP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS70145PWP reliable?
The price and inventory of TPS70145PWP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS70145PWP is usually 5 days.
3.What payment methods are accepted for TPS70145PWP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS70145PWP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS70145PWP?
TPS70145PWP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS70145PWP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS70145PWP?
For technical support, including TPS70145PWP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS70145PWP requirements.
6.How does Aetrix verify that TPS70145PWP is sourced from the original manufacturer or authorized distributors?
All TPS70145PWP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS70145PWP meets industry standards.
7.What is the process for return or replacement of TPS70145PWP?
All TPS70145PWP units undergo pre-shipment inspection (PSI). If there is an issue with TPS70145PWP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS70145PWP part is unused and in its original packaging.
Return procedure for TPS70145PWP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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