Texas Instruments TPS70348PWP

Overview

TPS70348PWP from Texas Instruments is a dual-output, low-dropout voltage regulator IC designed for split-voltage DSP and processor power systems. It delivers fixed 3.3 V/1.5 V outputs with independent enable control, 1 A on Regulator 1 and 2 A on Regulator 2, fast transient response, and integrated power-on reset (RESET) with 120 ms delay - used in TI C6000 DSP power sequencing applications.

For engineers reviewing the TPS70348PWP datasheet, TPS70348PWP pinout, TPS70348PWP application, or TPS70348PWP equivalent, key selection considerations include output voltage pairing (3.3 V/1.5 V), sequencing control via SEQ pin, thermal performance in HTSSOP-24 PowerPAD™ package, and SVS supervision of both regulators.

Technical Context

The TPS70348PWP integrates two PMOS-based LDOs with independent input rails (VIN1/VIN2), enabling flexible power domain isolation. Its sequencing logic uses an internal 6 mA pull-up on SEQ to determine power-up order: high/float enables VOUT2-first (1.5 V), low enables VOUT1-first (3.3 V).

It embeds dual supervisory functions: PG1 monitors VOUT1 at 95% threshold with 0.5% hysteresis and rising-edge deglitch (30 ms), while RESET asserts active-low after 120 ms when VIN1 > UVLO, MR pins inactive, and VOUT2 > 95% - all implemented without external components.

Key Specifications

Pinout & Package

TPS70348PWP is housed in a 24-pin HTSSOP package with exposed PowerPAD™ thermal pad (PWP designation). The package provides enhanced thermal dissipation (3.067 W at 0 CFM) and requires PCB copper pour under the pad per SLMA002 guidelines.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-output LDO regulator applications.

Compared with TPS70348PWP, TPS70351PWP shifts the secondary output to 1.8 V for modern logic families, while TPS70345PWP lowers it to 1.2 V for energy-constrained cores - both retain identical sequencing control, supervision timing, and thermal behavior in the same HTSSOP-24 PowerPAD™ package.

Availability

TPS70348PWP is available at Aetrix Electronics and suitable for TI DSP power sequencing, FPGA dual-rail supply, and industrial sensor hub applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for TPS70348PWP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog and embedded processing technologies, with leadership in power management ICs for industrial, automotive, and communications markets.

The TPS703xx family was engineered specifically for TI's DSP platforms, integrating dual LDOs, sequencing logic, and SVS supervision to replace multi-component discrete power solutions in high-reliability embedded systems.

FAQ

What output voltages does the TPS70348PWP provide?

The TPS70348PWP provides fixed 3.3 V on Regulator 1 (VOUT1) and fixed 1.5 V on Regulator 2 (VOUT2). These values are factory-trimmed and require no external feedback resistors. The 3.3 V/1.5 V pairing is optimized for TI C6000 DSP core-and-I/O configurations, and the TPS70348PWP datasheet confirms ±2% accuracy across load and temperature.

How does the SEQ pin control power-up sequencing on the TPS70348PWP?

On the TPS70348PWP, the SEQ pin determines which regulator powers up first: when SEQ is high or floating, VOUT2 (1.5 V) turns on first and VOUT1 (3.3 V) follows only after VOUT2 reaches ~83% of regulation; when SEQ is pulled low, VOUT1 powers up first. This behavior is implemented via internal logic and requires no external components - a key feature confirmed in the TPS70348PWP functional description.

What is the purpose of the RESET and PG1 pins on the TPS70348PWP?

The RESET pin on the TPS70348PWP is an open-drain SVS output that asserts low after a 120 ms delay when VIN1 exceeds UVLO, MR1/MR2 are inactive, and VOUT2 reaches ≥95% of 1.5 V. PG1 is an open-drain power-good signal tied exclusively to VOUT1 (3.3 V), going high-Z at ≥95% regulation. Both signals are documented in the TPS70348PWP terminal functions table and timing diagrams.

Can the TPS70348PWP operate with different input voltages on VIN1 and VIN2?

Yes - the TPS70348PWP supports independent input supplies: VIN1 (for 3.3 V regulator) and VIN2 (for 1.5 V regulator) may be sourced from separate rails. Recommended operating conditions specify VIN1/VIN2 between 2.7 V and 6 V, with UVLO thresholds at 2.3–2.65 V. This dual-input architecture is explicitly defined in the TPS70348PWP absolute maximum ratings and recommended operating conditions tables.

What thermal management is required for the TPS70348PWP in high-current operation?

The TPS70348PWP uses an HTSSOP-24 PowerPAD™ package (PWP) requiring soldering of the exposed thermal pad to a dedicated PCB copper pour. At 0 CFM airflow, its dissipation rating is 3.067 W with 30.67 mW/°C derating above +25°C. TI technical brief SLMA002 specifies the recommended 4-layer PCB layout with 1 oz. copper and 4-in × 4-in ground plane - all thermal data is validated and published in the TPS70348PWP datasheet's dissipation ratings table.