Texas Instruments TPS70358PWP

Overview

TPS70358PWP from Texas Instruments is a dual-output, low-dropout voltage regulator IC designed for split-voltage DSP and processor power systems. It delivers fixed 3.3 V/2.5 V outputs with independent enable control, 1 A on Regulator 1 and 2 A on Regulator 2, and integrated power-on reset (RESET) and power-good (PG1) functions - used in TI C6000 DSP power sequencing applications.

For engineers reviewing the TPS70358PWP datasheet, TPS70358PWP pinout, TPS70358PWP application, or TPS70358PWP equivalent, key selection criteria include output sequencing control via SEQ pin, ±2% output accuracy over load and temperature, 160 mV typical dropout at 1 A, ultralow 185 µA quiescent current, and thermal shutdown protection in HTSSOP-24 PowerPAD™ package.

Technical Context

The TPS70358PWP integrates two PMOS-based LDO regulators with independent input rails (VIN1/VIN2), enabling flexible power domain isolation. Its sequencing logic responds to the SEQ pin state: high or open enables VOUT2-first startup (83% threshold), while low enables VOUT1-first startup.

It embeds an SVS (supervisory circuit) with 120 ms RESET delay, active-low open-drain RESET and PG1 outputs, dual manual reset inputs (MR1/MR2), and undervoltage lockout (UVLO) on both inputs (2.3–2.65 V threshold). Bias is powered solely by VIN1.

Key Specifications

Pinout & Package

TPS70358PWP uses the 24-pin HTSSOP PowerPAD™ (PWP) package with exposed thermal pad connected to GND. The package includes four dedicated GND/HEATSINK terminals (pins 1, 12, 13, 24) for enhanced thermal performance and noise immunity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-output LDO regulator applications.

Compared with TPS70358PWP, TPS70351PWP and TPS70348PWP retain identical sequencing control, supervision timing, thermal performance, and package - differing only in VOUT2 voltage level to match specific core voltage requirements across DSP, FPGA, and ASIC platforms.

Availability

TPS70358PWP is available at Aetrix Electronics and suitable for DSP power sequencing, FPGA dual-rail supply, and industrial processor board applications requiring stable component supply, long-lifecycle support, and guaranteed traceability.

Supply support for TPS70358PWP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in high-reliability power solutions for industrial and computing markets.

The TPS703xx family was engineered specifically for TI DSP and processor power systems, integrating dual LDOs, sequencing logic, and supervisory functions to eliminate discrete support components and reduce board space in high-performance digital systems.

FAQ

What output voltages does the TPS70358PWP provide?

The TPS70358PWP provides fixed 3.3 V on Regulator 1 (VOUT1) and fixed 2.5 V on Regulator 2 (VOUT2). These are factory-trimmed outputs requiring no external feedback resistors. Both outputs maintain ±2% accuracy across load, line, and temperature (–40°C to +125°C), making TPS70358PWP ideal for precision DSP and FPGA power domains where voltage margin is critical.

How does the SEQ pin control power-up sequencing in the TPS70358PWP?

The SEQ pin on the TPS70358PWP determines which regulator powers up first: when SEQ is high or left open, VOUT2 (2.5 V) turns on first and VOUT1 (3.3 V) activates only after VOUT2 reaches ~83% of its nominal voltage; pulling SEQ low reverses this order. This programmable sequencing is implemented entirely within the TPS70358PWP die, eliminating external timers or logic - a key feature for TI DSP boot compliance.

What is the purpose of the PG1 and RESET pins on the TPS70358PWP?

PG1 is an open-drain output indicating VOUT1 status: it goes high-impedance when VOUT1 ≥ 95% of 3.3 V and low-impedance if it drops below that threshold. RESET is an open-drain SVS output that asserts low after a 120 ms delay once VIN1 exceeds UVLO and VOUT2 ≥ 95% of 2.5 V. Both signals require external pull-up resistors and are used for system-level power monitoring and initialization in TPS70358PWP-based designs.

Can the TPS70358PWP operate with different input voltages on VIN1 and VIN2?

Yes - the TPS70358PWP supports independent input supplies: VIN1 powers Regulator 1 (3.3 V) and internal bias, while VIN2 powers Regulator 2 (2.5 V). Recommended input ranges are 2.7–6 V for both, but they may differ (e.g., 3.3 V on VIN1, 5 V on VIN2). This separation allows domain-specific input sourcing and improves fault containment, a design advantage confirmed in the TPS70358PWP datasheet and application schematics.

What thermal performance can be expected from the TPS70358PWP in the PWP package?

In the HTSSOP-24 PowerPAD™ (PWP) package, the TPS70358PWP achieves up to 3.067 W power dissipation at TA ≤ +25°C with zero airflow, derating at 30.67 mW/°C. With 250 CFM airflow, dissipation rises to 4.115 W. The four GND/HEATSINK pins (1,12,13,24) must be soldered to a minimum 4-in × 4-in, 1 oz. copper ground plane per TI SLMA002 guidelines to realize this performance - essential for sustaining full 1 A/2 A loads in industrial TPS70358PWP deployments.