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Texas Instruments TPS70402PWP
- Part No.:
- TPS70402PWP
- Manufacturer:
- Texas Instruments
- Package:
- 24-PowerTSSOP (0.173", 4.40mm Width)
- Datasheet:
-
TPS70402PWP.pdf
- Description:
- IC REG LIN POS ADJ 24HTSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:363
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Product details
Overview
TPS70402PWP from Texas Instruments is a dual-output, adjustable low-dropout voltage regulator with integrated power-on reset (RESET), manual reset (MR), and dual open-drain power-good (PG1/PG2) outputs. It delivers up to 1 A on regulator 1 and 2 A on regulator 2, features 185 µA typical quiescent current, 2% output accuracy over load and temperature, and operates from –40°C to +125°C in split-voltage systems for FPGA core/I/O rail sequencing.
For engineers reviewing the TPS70402PWP datasheet, TPS70402PWP pinout, TPS70402PWP application, or TPS70402PWP equivalent, key selection considerations include independent enable control (EN1/EN2), dual feedback (FB1/FB2) for adjustable outputs, thermal shutdown protection, 120-ms RESET delay, and compatibility with 47-µF low-ESR output capacitors without external bypass.
Technical Context
The TPS70402PWP uses PMOS pass transistors for both regulators, enabling ultralow, load-independent quiescent current (max 250 µA) and low dropout voltage (160 mV typ at 1 A for Reg1). Its internal bias is powered solely by VIN1, requiring ≥2.7 V for full functionality.
Each regulator includes dedicated undervoltage lockout (UVLO), fast transient response optimized for 47-µF ceramic capacitors, and independent discharge transistors that actively sink output capacitance when disabled. The RESET output is active-low, open-drain, with 120-ms delay after VIN1 exceeds UVLO and MR is high-impedance.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Configuration | Dual independent LDOs: Reg1 (1 A max), Reg2 (2 A max), both adjustable via FB1/FB2 |
| Quiescent Current | 185 µA typ (full load); remains stable across 0–1 A (Reg1) and 0–2 A (Reg2) - enables battery-sensitive designs |
| Dropout Voltage | 160 mV typ at 1 A (Reg1); enables operation with minimal input–output margin (e.g., 3.3-V out from 3.46-V input) |
| Accuracy | ±2% over full load, line, and temperature (–40°C to +125°C) - ensures reliable voltage margins for core logic |
| Power-Good Outputs | PG1 and PG2 are open-drain, active-high, trip at 95% VOUT with 30-ms deglitch - provide precise rail monitoring for system sequencing |
| RESET Function | Active-low open-drain with 120-ms fixed delay; asserts only after VIN1 > 2.65 V and MR high - eliminates false resets during brown-in |
| Noise Performance | 79 µVRMS (Reg1), 77 µVRMS (Reg2), measured 300 Hz–50 kHz without bypass capacitor - reduces need for noise-filtering components |
Pinout & Package
Packaged in HTSSOP-24 (PWP) with exposed PowerPAD™ thermal pad (pins 1, 12, 13, 24 serve as GND/heatsink).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN1 (pins 2,3) | Input supply for regulator 1 | Must be ≥2.7 V; powers internal bias circuitry - single point of control for entire device |
| VIN2 (pins 10,11) | Input supply for regulator 2 | Independent of VIN1; supports split-input architectures (e.g., separate 5-V and 3.3-V sources) |
| VOUT1 (pins 22,23) | Regulator 1 output | Delivers up to 1 A; dual pins reduce IR drop and improve thermal performance |
| VOUT2 (pins 14,15) | Regulator 2 output | Delivers up to 2 A; dual pins support high-current digital I/O rails |
| FB1 (pin 21) | Feedback input for regulator 1 | Connects to resistor divider for adjustable output (1.22–5.5 V); high-impedance input minimizes loading |
| FB2 (pin 16) | Feedback input for regulator 2 | Independent adjustment range (1.22–5.5 V); enables asymmetric rail configurations (e.g., 1.2 V core / 3.3 V interface) |
| EN1 (pin 6), EN2 (pin 7) | Active-low enable inputs | Enable/disable each regulator independently - supports flexible power sequencing without external logic |
| PG1 (pin 19), PG2 (pin 18) | Open-drain power-good indicators | Assert high-impedance when respective VOUT reaches 95% - used for FPGA configuration lock or processor reset hold-off |
| RESET (pin 8) | Open-drain system reset output | Active-low, 120-ms delayed assertion - directly drives microcontroller / FPGA reset pins with no external timing components |
| MR (pin 5) | Manual reset input | Active-low; internally pulled up to VIN1 with 6 mA - allows external pushbutton or supervisor IC to force system reset |
| GND/HEATSINK (pins 1,12,13,24) | Ground reference and thermal path | Exposed PowerPAD requires PCB copper pour for thermal dissipation - critical for >1 W continuous operation |
| NC (pins 4,17,20) | No internal connection | Must remain unconnected - floating or tied to GND may cause parasitic coupling or EMI |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent enable (EN1/EN2) | Enables staggered startup/shutdown of core and I/O rails - eliminates need for external sequencers in FPGA/CPU power trees |
| Integrated 120-ms RESET with UVLO gating | Guarantees clean system reset only after stable VIN1 - prevents premature boot under marginal input conditions |
| Active output discharge (Reg1/Reg2) | Internally sinks VOUT capacitance when disabled - ensures rapid rail collapse for safe state transitions in hot-swap applications |
| PMOS pass architecture | Maintains <250 µA quiescent current across full load range - extends battery life in portable instrumentation |
| Thermal shutdown + UVLO on both inputs | Protects against overtemperature and undervoltage faults without external supervision - reduces BOM count in industrial controllers |
Applications
| FPGA Core & I/O Rail Sequencing | Industrial PLC Power Management |
|---|---|
Use Scenario: Powering Xilinx Artix-7 FPGA with 1.2-V core and 3.3-V I/O banks requiring strict voltage sequencing and rail monitoring. IC Role / Device Role / Timing Role: Dual-LDO regulator providing independent, adjustable outputs with synchronized PG signals and programmable RESET delay. Use Value: Eliminates external sequencing ICs; PG1/PG2 enable FPGA configuration lock until both rails stabilize; RESET ensures deterministic boot after power recovery. | Use Scenario: Supplying isolated microcontroller (1.8 V), CAN transceiver (3.3 V), and analog sensor front-end (2.5 V) in a DIN-rail mounted PLC. IC Role / Device Role / Timing Role: Centralized dual-output LDO with MR input for emergency reset and RESET output for watchdog-triggered recovery. Use Value: Single-chip solution replaces three discrete regulators + supervisor; MR pin accepts panel-mounted reset button; thermal shutdown protects against enclosure overheating. |
| Automotive Infotainment SoC Supply | Medical Imaging Sensor Bias |
Use Scenario: Delivering 1.1-V CPU core and 1.8-V GPU voltage to a TI Jacinto processor in automotive head unit, operating from 5-V DC-DC converter. IC Role / Device Role / Timing Role: Adjustable dual-LDO with independent EN1/EN2 for dynamic power gating and PG outputs for SoC power-state coordination. Use Value: Enables deep-sleep mode (2 mA standby) when both EN pins asserted; fast transient response maintains voltage during burst-mode GPU operation. | Use Scenario: Providing ultra-low-noise 2.05-V bias for CMOS image sensor array in portable ultrasound probe, where EMI must be minimized. IC Role / Device Role / Timing Role: Low-noise dual-LDO (77 µVRMS) with FB2-adjusted output and active discharge for rapid sensor power cycling. Use Value: No external bypass capacitor required; discharge transistor clears residual charge before next frame capture - prevents image ghosting. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output LDO regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS70451PWP | Fixed 3.3-V/1.8-V outputs; no FB pins; identical pinout and package | Eliminates external feedback resistors but lacks output flexibility - suitable only for standard rail combinations | Select when design uses only 3.3 V/1.8 V and board space is constrained; no layout change needed |
| TPS7A8300RGWR | Single-channel, 3-A adjustable LDO; no integrated RESET/PG; 16-pin QFN | Requires two devices for dual-rail support; lacks system-level supervision features | Choose for higher current per rail (>2 A) or when external sequencing logic already exists |
Compared with TPS70451PWP and TPS7A8300RGWR, the TPS70402PWP uniquely combines dual adjustable outputs, integrated RESET/PG/MR, and thermal protection in one 24-pin HTSSOP - reducing component count and enabling compact, self-monitored power solutions for complex SoCs.
Availability
TPS70402PWP is available at Aetrix Electronics and suitable for FPGA power sequencing, industrial PLCs, automotive infotainment systems, and medical imaging equipment requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for TPS70402PWP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in power management ICs.
The TPS704xx family was designed specifically for split-rail digital systems requiring precise, sequenced, and supervised dual-voltage regulation - targeting FPGA, ASIC, and multicore processor applications where reliability and integration are critical.
FAQ
What output voltage ranges does the TPS70402PWP support?
The TPS70402PWP supports adjustable outputs from 1.22 V to 5.5 V on both regulators via external resistor dividers connected to FB1 and FB2. Unlike fixed-output variants (e.g., TPS70451), it does not preset voltages - enabling custom rail configurations such as 1.2 V core / 2.5 V analog or 1.8 V DSP / 3.3 V interface. Minimum input voltage is VO(typ) + 1 V or 2.7 V, whichever is greater.
How does the TPS70402PWP handle power sequencing between its two outputs?
TPS70402PWP does not enforce automatic sequencing - EN1 and EN2 are independent active-low enables, allowing designers to control startup order externally via GPIO or RC delays. PG1 and PG2 provide status feedback, while RESET offers a system-level reset signal triggered only after VIN1 stabilizes and MR is released. This architecture gives full sequencing flexibility without fixed timing constraints.
Can the TPS70402PWP operate with ceramic output capacitors only?
Yes, the TPS70402PWP is stable with 47-µF low-ESR ceramic capacitors on VOUT2 and 22-µF on VOUT1, as specified in the datasheet. It does not require tantalum or electrolytic capacitors. The device's PMOS architecture and internal compensation eliminate need for external bypass capacitors - verified by 77–79 µVRMS noise performance without added filtering.
What is the function of the GND/HEATSINK pins on the TPS70402PWP?
The four GND/HEATSINK pins (1, 12, 13, 24) connect to the exposed PowerPAD™ thermal pad beneath the HTSSOP-24 package. They serve dual roles: providing low-impedance ground return paths and conducting heat into the PCB copper pour. TI specifies a 4-layer board with 1 oz. copper and 4-in × 4-in ground plane for rated 3.067 W dissipation at 25°C ambient - omitting proper thermal land compromises SOA and long-term reliability.
Does the TPS70402PWP include overcurrent protection?
The TPS70402PWP includes current limiting but not foldback or hiccup-mode protection. Regulator 1 limits at 1.75–2.2 A (typ), Regulator 2 at 3.8–4.5 A (typ), with thermal shutdown activating at +150°C junction temperature. Under sustained overload, the device enters thermal shutdown and recovers automatically once cooled - no latch-up or manual reset required. Peak current ratings assume 2-ms pulse width.
TPS70402PWP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 24-PowerTSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Output Configuration:
- Positive
- Output Type:
- Adjustable
- Number of Regulators:
- 2
- Voltage - Input (Max):
- 6V
- Voltage - Output (Min/Fixed):
- 1.22V
- Voltage - Output (Max):
- 5.5V
- Voltage Dropout (Max):
- 0.25V @ 1A, -
- Current - Output:
- 1A, 2A
- Current - Quiescent (Iq):
- 250 µA
- Current - Supply (Max):
- -
- PSRR:
- 65dB (1kHz), 60dB (1kHz)
- Control Features:
- Enable, Power Good, Reset, Sequencing
- Protection Features:
- Over Current, Over Temperature, Reverse Polarity, Under Voltage Lockout (UVLO)
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-HTSSOP
TPS70402PWP FAQ
1.How can I place an order for TPS70402PWP through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS70402PWP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS70402PWP reliable?
The price and inventory of TPS70402PWP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS70402PWP is usually 5 days.
3.What payment methods are accepted for TPS70402PWP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS70402PWP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS70402PWP?
TPS70402PWP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS70402PWP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS70402PWP?
For technical support, including TPS70402PWP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS70402PWP requirements.
6.How does Aetrix verify that TPS70402PWP is sourced from the original manufacturer or authorized distributors?
All TPS70402PWP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS70402PWP meets industry standards.
7.What is the process for return or replacement of TPS70402PWP?
All TPS70402PWP units undergo pre-shipment inspection (PSI). If there is an issue with TPS70402PWP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS70402PWP part is unused and in its original packaging.
Return procedure for TPS70402PWP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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