Texas Instruments TPS70458PWP
- Part No.:
- TPS70458PWP
- Manufacturer:
- Texas Instruments
- Package:
- 24-PowerTSSOP (0.173", 4.40mm Width)
- Datasheet:
-
TPS70458PWP.pdf
- Description:
- IC REG LINEAR 3.3V/2.5V 24HTSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:122
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Product details
Overview
TPS70458PWP from Texas Instruments is a dual-output, low-dropout voltage regulator IC delivering fixed 3.3 V (1 A) and 2.5 V (2 A) outputs with integrated power-on reset (RESET), power-good (PG1/PG2), and independent enable inputs (EN1/EN2). It features 185 µA typical quiescent current, 160 mV dropout at 1 A on Regulator 1, and operates across –40°C to +125°C in split-voltage systems such as DSP/FPGA core-I/O power domains.
For engineers reviewing the TPS70458PWP datasheet, TPS70458PWP pinout, TPS70458PWP application, or TPS70458PWP equivalent, key selection considerations include dual-rail sequencing capability, ±2% output accuracy over load/temperature, 120-ms RESET delay, open-drain PG monitoring for both rails, and thermal shutdown protection in the HTSSOP-24 PowerPAD™ package.
Technical Context
The TPS70458PWP integrates two independent PMOS-based LDO regulators with separate input pins (VIN1/VIN2), enabling flexible power domain isolation. Each regulator uses internal voltage-sense feedback (VSENSE1/VSENSE2) tied to its respective output, supporting fast transient response (<10 µs recovery) with 47 µF low-ESR capacitors.
Its supervisory functions include an active-low open-drain RESET with 120-ms delay triggered after VIN1 exceeds 2.65 V UVLO threshold and MR pin release; PG1 and PG2 independently monitor VOUT1 and VOUT2 at 95% trip points with 30-ms deglitching and require external pull-up resistors.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output voltages | Fixed 3.3 V (Reg1, 1 A max) and 2.5 V (Reg2, 2 A max); enables I/O-core split supply without external feedback resistors. |
| Dropout voltage | 160 mV typ at 1 A (Reg1), 250 mV max; allows operation with minimal headroom-e.g., 3.2 V input sustains 3.3 V output. |
| Quiescent current | 185 µA typ at full load; remains stable across 0–1 A (Reg1) and 0–2 A (Reg2), reducing standby power loss. |
| Accuracy | ±2% over full load and temperature (–40°C to +125°C); ensures reliable logic-level compliance for 3.3 V and 2.5 V interfaces. |
| RESET delay | 120 ms typ after valid VIN1 and MR release; provides deterministic power-on sequencing for downstream processors. |
| Power-good thresholds | PG1/PG2 assert high-Z when VOUT ≥95% nominal; hysteresis of 0.5% prevents chatter during marginal conditions. |
| Thermal protection | Thermal shutdown activates at TJ = +150°C; auto-recovery upon cooling supports robust operation in enclosed environments. |
Pinout & Package
TPS70458PWP is housed in a 24-pin HTSSOP package (PWP) with exposed thermal pad (PowerPAD™) for enhanced heat dissipation. The package measures 7.8 mm × 4.4 mm × 1.2 mm and requires PCB copper pour under the pad per TI SLMA002 guidelines.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN1 (pins 2,3) | Input for Regulator 1 | Supplies 3.3 V rail; powers internal bias circuitry; must be ≥2.7 V for full functionality. |
| VIN2 (pins 10,11) | Input for Regulator 2 | Supplies 2.5 V rail; independent of VIN1, enabling mixed-input architectures (e.g., 5 V + 3.3 V sources). |
| VOUT1 (pins 22,23) | Output of Regulator 1 | Delivers up to 1 A at 3.3 V; dual pins reduce IR drop and improve current sharing. |
| VOUT2 (pins 14,15) | Output of Regulator 2 | Delivers up to 2 A at 2.5 V; dual pins support high-current FPGA I/O banks. |
| EN1 (pin 6), EN2 (pin 7) | Enable controls | Active-low inputs; pulling either low disables its regulator, reducing IQ to 2 mA total in sleep mode. |
| PG1 (pin 19), PG2 (pin 18) | Power-good indicators | Open-drain outputs signaling regulation status; require external pull-up for system monitoring or sequencing logic. |
| RESET (pin 8) | Supervisory reset signal | Active-low open-drain output; asserts after 120-ms delay when VIN1 >2.65 V and MR is high. |
| MR (pin 5) | Manual reset input | Active-low input with 6 mA internal pull-up to VIN1; connects to PG1/PG2 for cascaded reset propagation. |
| GND/HEATSINK (pins 1,12,13,24) | Ground & thermal path | Four dedicated ground pins plus thermal pad provide low-inductance return and efficient heat transfer to PCB. |
| VSENSE1 (pin 21), VSENSE2 (pin 16) | Voltage sense inputs | Internally connected to outputs in fixed-voltage mode; must be shorted directly to VOUT1/VOUT2 for accuracy. |
| NC (pins 4,17,20) | No connection | Unbonded pins; must remain unconnected to avoid parasitic coupling or ESD risk. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent enable inputs | EN1 and EN2 allow staggered startup/shutdown of 3.3 V and 2.5 V rails-critical for FPGA configuration sequencing. |
| Integrated 120-ms power-on reset | Eliminates need for external RC timing networks; ensures deterministic processor reset after stable input voltage. |
| Low-noise operation (77–79 mVRMS) | Meets noise-sensitive analog supply requirements without bypass capacitors, simplifying BOM and layout. |
| Quick output capacitor discharge | Internal discharge transistors pull VOUT1/VOUT2 to GND when disabled, preventing back-powering of downstream circuits. |
| UVLO with hysteresis (2.4–2.65 V) | Prevents erratic regulator behavior during brownout; 110 mV hysteresis avoids oscillation near threshold. |
Applications
| Baseband Processor Power | FPGA Core/I/O Supply |
|---|---|
Use Scenario: Powering cellular baseband processors requiring tightly regulated 3.3 V I/O and 2.5 V core rails with synchronized reset assertion. IC Role / Device Role / Timing Role: Dual-LDO regulator providing independent, sequenced voltage domains and generating a system-wide RESET signal after stable input. Use Value: Eliminates discrete reset IC and reduces component count by integrating PG monitoring and 120-ms delay into single package. | Use Scenario: Supplying Xilinx Spartan-6 FPGA with 2.5 V I/O banks and 1.2 V core-using TPS70458PWP's 3.3 V/2.5 V outputs as pre-regulators feeding DC-DC converters. IC Role / Device Role / Timing Role: Primary linear regulator delivering clean, low-noise intermediate rails; PG1/PG2 feed FPGA INIT_B and CCLK for safe configuration. Use Value: ±2% accuracy ensures I/O voltage stays within FPGA VIH/VIL specs; fast transient response handles dynamic I/O switching loads. |
| DSP + Memory Subsystem | Industrial PLC Controller |
Use Scenario: Powering TI C6000 DSP and DDR2 memory interface where 3.3 V data bus and 2.5 V memory termination require simultaneous regulation and fault reporting. IC Role / Device Role / Timing Role: Dual-output LDO supplying parallel voltage domains while PG2 monitors DDR2 VTT stability and triggers system alert if violated. Use Value: Independent PG outputs enable granular fault isolation-e.g., PG2 low indicates memory rail failure without affecting DSP operation. | Use Scenario: Providing redundant 3.3 V control logic and 2.5 V sensor interface rails in DIN-rail mounted PLCs operating from 24 V DC input. IC Role / Device Role / Timing Role: Main power management IC delivering isolated, thermally robust outputs; RESET coordinates firmware boot after 24 V input stabilization. Use Value: PowerPAD™ package and thermal shutdown enable continuous 2 A operation at +85°C ambient-meeting industrial temperature requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output LDO regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS70451PWP | Outputs 3.3 V / 1.8 V instead of 3.3 V / 2.5 V; identical pinout, package, and feature set. | Suitable for 1.8 V core logic (e.g., ARM Cortex-M4) rather than 2.5 V interfaces or memory. | Select TPS70451PWP when target SoC requires 1.8 V core voltage; no PCB changes needed. |
| TPS70448PWP | Outputs 3.3 V / 1.5 V; same thermal performance, quiescent current, and supervision features. | Optimized for ultra-low-voltage digital cores (e.g., ASICs with 1.5 V domains) where 2.5 V is not required. | Choose TPS70448PWP for 1.5 V core applications; shares footprint and layout with TPS70458PWP. |
Compared with TPS70451PWP and TPS70448PWP, the TPS70458PWP uniquely supports 2.5 V I/O standards (e.g., PCI-X, older FPGAs) while maintaining identical sequencing, supervision, and thermal characteristics-making it the optimal choice for legacy interface compatibility.
Availability
TPS70458PWP is available at Aetrix Electronics and suitable for industrial automation, telecommunications infrastructure, and embedded computing applications requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for TPS70458PWP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in precision voltage regulation and power integrity solutions.
The TPS704xx family was designed specifically for split-voltage digital systems-delivering dual, independently enabled LDOs with integrated power sequencing, reset, and monitoring to simplify power architecture in DSP, FPGA, and microprocessor applications.
FAQ
What are the exact output voltages and current capabilities of the TPS70458PWP?
The TPS70458PWP delivers fixed 3.3 V at up to 1 A on Regulator 1 and fixed 2.5 V at up to 2 A on Regulator 2. Both outputs maintain ±2% accuracy across –40°C to +125°C and full load range. The 3.3 V rail uses VIN1, while the 2.5 V rail uses VIN2-enabling independent input sourcing. Dropout is 160 mV typ at 1 A for Regulator 1, allowing operation from as low as 3.46 V input.
How does the RESET function operate on the TPS70458PWP, and what conditions trigger it?
The RESET pin on the TPS70458PWP is an active-low, open-drain output that asserts after a 120-ms delay when two conditions are met: VIN1 exceeds 2.65 V (UVLO threshold) and the MR pin is released (high-impedance or pulled high). RESET remains asserted if MR is pulled low or VIN1 drops below 2.4 V. An external pull-up resistor is required for proper logic-level operation.
Can the TPS70458PWP be used with different input voltages for each regulator, and what are the minimum input requirements?
Yes-the TPS70458PWP supports independent inputs: VIN1 (pins 2,3) for the 3.3 V regulator and VIN2 (pins 10,11) for the 2.5 V regulator. Minimum input is 2.7 V for VIN1 (to power internal bias) and VO + 1 V for each regulator-i.e., ≥4.3 V for VIN1 and ≥3.5 V for VIN2. Inputs up to 6 V are allowed, with dropout scaling linearly with load current.
What is the purpose of the VSENSE1 and VSENSE2 pins on the TPS70458PWP, and how should they be connected?
On the TPS70458PWP, VSENSE1 (pin 21) and VSENSE2 (pin 16) are voltage-sense inputs tied internally to the feedback network. For fixed-output operation, they must be connected directly to VOUT1 and VOUT2 respectively-using short, low-impedance traces. This Kelvin sensing improves regulation accuracy by rejecting PCB trace resistance effects and minimizing noise coupling into the error amplifier.
Does the TPS70458PWP include thermal protection, and what happens when it activates?
Yes, the TPS70458PWP includes thermal shutdown protection that activates at a junction temperature of +150°C. When triggered, both regulators shut down immediately to prevent damage. The device remains latched off until junction temperature falls below the hysteresis threshold (~140°C), at which point regulation resumes automatically-no external reset is required. This protects against sustained overload or poor heatsinking in compact enclosures.
TPS70458PWP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 24-PowerTSSOP (0.173", 4.40mm Width)
- Packaging:
- Bulk
- Product Status:
- Active
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 2
- Voltage - Input (Max):
- 6V
- Voltage - Output (Min/Fixed):
- 3.3V, 2.5V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.25V @ 1A, -
- Current - Output:
- 1A, 2A
- Current - Quiescent (Iq):
- 250 µA
- Current - Supply (Max):
- -
- PSRR:
- 65dB (1kHz), 60dB (1kHz)
- Control Features:
- Enable, Power Good, Reset, Sequencing
- Protection Features:
- Over Current, Over Temperature, Reverse Polarity, Under Voltage Lockout (UVLO)
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-HTSSOP
TPS70458PWP FAQ
1.How can I place an order for TPS70458PWP through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS70458PWP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS70458PWP reliable?
The price and inventory of TPS70458PWP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS70458PWP is usually 5 days.
3.What payment methods are accepted for TPS70458PWP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS70458PWP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS70458PWP?
TPS70458PWP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS70458PWP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS70458PWP?
For technical support, including TPS70458PWP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS70458PWP requirements.
6.How does Aetrix verify that TPS70458PWP is sourced from the original manufacturer or authorized distributors?
All TPS70458PWP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS70458PWP meets industry standards.
7.What is the process for return or replacement of TPS70458PWP?
All TPS70458PWP units undergo pre-shipment inspection (PSI). If there is an issue with TPS70458PWP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS70458PWP part is unused and in its original packaging.
Return procedure for TPS70458PWP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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