My Inquiry
My Account
Texas Instruments TPS71334DRCT
- Part No.:
- TPS71334DRCT
- Manufacturer:
- Texas Instruments
- Package:
- 10-VFDFN Exposed Pad
- Datasheet:
-
TPS71334DRCT.pdf
- Description:
- IC REG LIN POS ADJ 250MA 10VSON
- Quantity:
- Payment:
- Shipping:
Inventory:231
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TPS71334DRCT from Texas Instruments is a dual-output, ultra-low-noise, high-PSRR low-dropout linear regulator with fixed 3.3 V output on CH1 and adjustable output (1.2 V–5.5 V) on CH2, integrated supply voltage supervisor (SVS) monitoring OUT2, 125 mV typical dropout at 250 mA per channel, and stable operation with 2.2 µF ceramic capacitors - deployed in RF front-ends and precision analog subsystems of wireless handhelds and digital cameras.
For engineers reviewing the TPS71334DRCT datasheet, TPS71334DRCT pinout, TPS71334DRCT application, or TPS71334DRCT equivalent, key selection criteria include dual-channel independent enable control, SVS-triggered open-drain RESET assertion at 95% VOUT2 with 50–200 ms delay, 32 µVrms output noise (with 0.01 µF NR capacitor), 65 dB PSRR at 10 kHz, and thermal shutdown at +160°C junction temperature.
Technical Context
The TPS71334DRCT integrates two PMOS-based LDOs sharing a common IN/GND rail but featuring independent EN1/EN2 enables, separate output paths, and dedicated feedback (FB2) for CH2. Its SVS circuit continuously monitors OUT2 voltage and asserts the open-drain RESET pin when VOUT2 falls below 92.5–97.5% of nominal, with 0.5% hysteresis and programmable delay via external RC.
Each LDO achieves fast 60 µs startup using internal quickstart logic that temporarily shorts the 250 kΩ NR-path resistor; noise reduction is implemented via an external capacitor on the NR pin, which filters the 1.225 V internal reference before it drives the error amplifier. The device operates across –40°C to +125°C junction temperature and supports full-spec performance with ≤2.2 µF ceramic output capacitance per channel.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Configuration | Dual independent LDOs: CH1 fixed at 3.3 V, CH2 adjustable (1.2 V–5.5 V) via FB2 resistor divider |
| Max Output Current | 250 mA per channel - sufficient to power RF transceivers, DSP cores, or FPGA I/O banks without external boost |
| Dropout Voltage | 125 mV typical at 250 mA - enables operation from 3.425 V input to sustain 3.3 V output under full load |
| Output Noise | 32 µVrms (10 Hz–100 kHz) with 0.01 µF NR capacitor - meets stringent requirements for PLL/VCO power rails |
| PSRR | 65 dB at 10 kHz - suppresses switching noise from adjacent DC/DC converters feeding shared input rails |
| RESET Threshold | 95% of VOUT2 with 0.5% hysteresis and 50–200 ms delay - provides reliable brownout detection for sequenced power-up of processors |
| Quiescent Current | 300 µA typical with both outputs enabled - minimizes standby power in battery-operated portable systems |
Pinout & Package
TPS71334DRCT is housed in a thermally enhanced 3 mm × 3 mm × 1 mm SON-10 (DRC) package with exposed thermal pad (Pin 5/PAD connected to GND). The package supports high-power-density layouts and achieves RθJA = 52°C/W on JEDEC High-K board.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN (Pin 1) | Unregulated input supply rail | Accepts 2.7–5.5 V; requires 0.1 µF ceramic bypass to GND near pin for stability and transient immunity |
| GND (Pins 5 & Pad) | Power and signal reference ground | Thermal pad must be soldered to PCB ground plane for thermal performance and EMI control |
| OUT1 (Pin 3) | Fixed 3.3 V regulated output | Stable with ≥2.2 µF ceramic capacitor; supplies noise-sensitive analog circuits or MCU cores |
| OUT2 (Pin 4) | Adjustable regulated output (1.2 V–5.5 V) | Set via external R1/R2 divider on FB2; supports processor I/O, memory, or peripheral rails |
| EN1 (Pin 10) | Active-high enable for CH1 | Drives high (>1.2 V) to activate OUT1; tie to IN if always-on; pulls low (<0.4 V) for <0.3 µA shutdown current |
| EN2 (Pin 8) | Active-high enable for CH2 | Independent control enables power sequencing - e.g., enable CH2 only after CH1 stabilizes |
| NR (Pin 6) | Noise reduction filter node | Connect 0.01 µF ceramic to GND to reduce reference noise; enables 32 µVrms output noise performance |
| RESET (Pin 2) | Open-drain SVS output | Asserts low when VOUT2 drops below threshold; requires external 10 kΩ–1 MΩ pull-up to valid logic voltage |
| FB2/NC (Pin 7) | CH2 feedback input / no-connect | Connect R1/R2 divider for adjustable VOUT2; leave floating only if CH2 unused (not recommended) |
| NC (Pin 9) | No connection | Not bonded; must remain unconnected and un-routed on PCB |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent enable pins | EN1 and EN2 allow precise power sequencing - e.g., delay CH2 activation until CH1 output reaches regulation |
| Integrated SVS with programmable delay | Monitors only OUT2 and asserts RESET with 50–200 ms delay; eliminates need for external supervisor IC |
| Ultra-low noise with NR pin | 32 µVrms output noise achieved via 0.01 µF capacitor on NR pin - critical for powering VCOs and ADC references |
| Stable with minimal output capacitance | Guaranteed stability with 2.2 µF X5R/X7R ceramic capacitors - reduces BOM cost and board area vs. tantalum solutions |
| Fast 60 µs startup time | Internal quickstart circuit shorts NR-path resistor for first 400 µs - enables rapid wake-up in low-power sensor nodes |
| Thermal shutdown with hysteresis | Shuts down both channels at +160°C junction temp; resumes at +140°C - prevents thermal runaway during overload |
Applications
| RF Transceiver Power Supply | DSP/FPGA Core & I/O Rail Sequencing |
|---|---|
Use Scenario: Powering LTE/Wi-Fi transceiver RFICs requiring clean, low-noise 3.3 V supply and independently sequenced 1.8 V I/O rail. IC Role / Device Role / Timing Role: TPS71334DRCT delivers ultra-low-noise 3.3 V to RF synthesizer and uses CH2 to generate 1.8 V for digital interface, with EN2 delayed via RC network to meet setup timing. Use Value: 32 µVrms noise ensures <–150 dBc phase noise floor; independent enables prevent bus contention during power-up. |
Use Scenario: Supplying dual-voltage domains for a Zynq-7000 SoC: 3.3 V for PS MIO and 1.0 V for PL core (via external DC/DC), with TPS71334DRCT generating 1.8 V for PS I/O banks. IC Role / Device Role / Timing Role: CH1 powers PS MIO; CH2 (set to 1.8 V) powers PS I/O; RESET monitors CH2 and holds PS reset until 1.8 V is valid. Use Value: Integrated SVS eliminates external supervisor; 65 dB PSRR at 10 kHz rejects noise from switching regulators feeding IN rail. |
| Digital Camera Image Signal Processor | Wireless PDA Baseband Subsystem |
Use Scenario: Providing regulated power to CMOS image sensor analog front-end (3.3 V) and ISP core logic (adjustable 1.2 V–1.5 V) in compact camera modules. IC Role / Device Role / Timing Role: TPS71334DRCT CH1 powers sensor analog circuitry; CH2 powers ISP digital logic; NR pin used to minimize switching artifacts in captured images. Use Value: 2.2 µF ceramic stability allows use of 0402/0603 caps in space-constrained modules; 125 mV dropout extends battery runtime. |
Use Scenario: Powering Bluetooth baseband IC (3.3 V) and application processor I/O (1.8 V) in handheld PDAs with tight thermal constraints. IC Role / Device Role / Timing Role: CH1 supplies BT radio; CH2 supplies AP I/O; thermal shutdown protects against enclosure overheating during sustained data transfer. Use Value: 3 mm × 3 mm SON package fits narrow PCB margins; 300 µA quiescent current extends standby time between sync events. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-LDO regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS71319DRCT | Fixed 1.8 V on CH1, adjustable CH2; same pinout, package, and SVS functionality | Targeted at lower-voltage SoCs (e.g., ARM Cortex-A5/A7) requiring 1.8 V core/I/O instead of 3.3 V analog rails | Select when system requires 1.8 V primary rail and maintains identical sequencing, noise, and thermal specs |
| TPS7A8300RGRT | Single-channel, 3 A, 7 µVrms noise, no SVS or dual output; 10-pin VQFN vs. DRC | Used where higher current or lower noise is needed for single-rail applications - not a drop-in replacement | Choose only if redesigning for single-rail, higher-current needs and can accommodate different pinout and no RESET function |
Compared with TPS71319DRCT, TPS71334DRCT provides higher CH1 output for analog/RF stages, while TPS7A8300RGRT trades dual output and SVS for ultra-low noise and higher current - making TPS71334DRCT optimal for space-constrained, dual-rail, supervisor-integrated designs.
Availability
TPS71334DRCT is available at Aetrix Electronics and suitable for RF transceiver power supplies, DSP/FPGA rail sequencing, digital camera ISP subsystems, and wireless PDA baseband designs requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for TPS71334DRCT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in high-reliability, high-performance power regulation solutions.
The TPS713xx family was designed specifically for noise-sensitive RF and portable applications - delivering dual LDOs with integrated SVS, ultra-low noise, and minimal external components in compact thermally enhanced packages.
FAQ
What is the maximum input voltage rating for the TPS71334DRCT?
The TPS71334DRCT has an absolute maximum input voltage (VIN) rating of 6.0 V. Operation above this level risks permanent damage. For reliable continuous operation, VIN must remain within 2.7 V to 5.5 V per the Electrical Characteristics table, with minimum VIN = VOUT(nom) + VDO or 2.7 V, whichever is greater - so for 3.3 V OUT1, minimum VIN is 3.425 V.
How does the RESET function monitor voltage in the TPS71334DRCT?
The RESET pin in the TPS71334DRCT is controlled solely by the SVS circuit monitoring OUT2. It asserts low when VOUT2 falls below 92.5–97.5% of its nominal value, with 0.5% hysteresis and a user-programmable delay (50–200 ms) set by external RC on the RESET line. It does not monitor OUT1 or IN.
Can the TPS71334DRCT operate with only one output enabled?
Yes - the TPS71334DRCT supports independent operation: EN1 controls OUT1 and EN2 controls OUT2. With only EN1 high, OUT1 delivers 3.3 V while OUT2 remains off and draws <0.3 µA total ground current. This enables flexible power partitioning in multi-sleep-state systems.
What capacitor value is required on the NR pin to achieve 32 µVrms noise in the TPS71334DRCT?
A 0.01 µF ceramic capacitor connected from the NR pin to GND is required to achieve the specified 32 µVrms output noise (10 Hz–100 kHz) in the TPS71334DRCT. Larger values increase startup time; smaller values degrade noise performance - 0.01 µF is the design-optimized value validated in TI's SBVS055A datasheet.
Is the TPS71334DRCT RoHS compliant and what is its moisture sensitivity level?
Yes, the TPS71334DRCT is RoHS compliant (lead-free, NIPDAU finish) and rated MSL Level-2-260°C-1 Year per JEDEC J-STD-020. This means it may be stored for up to 1 year at ≤30°C/60% RH before reflow, and requires peak reflow temperature ≤260°C - standard for automated SMT assembly.
TPS71334DRCT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 10-VFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Output Configuration:
- Positive
- Output Type:
- Adjustable (Fixed)
- Number of Regulators:
- 2
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 1.2V (3.3V)
- Voltage - Output (Max):
- 5.5V
- Voltage Dropout (Max):
- 0.4V @ 500mA
- Current - Output:
- 250mA
- Current - Quiescent (Iq):
- 250 µA
- Current - Supply (Max):
- 600 µA
- PSRR:
- 59dB ~ 54dB (120Hz)
- Control Features:
- Enable, Power Good
- Protection Features:
- Over Temperature, Reverse Polarity, Under Voltage Lockout (UVLO)
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-VSON (3x3)
TPS71334DRCT FAQ
1.How can I place an order for TPS71334DRCT through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS71334DRCT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS71334DRCT reliable?
The price and inventory of TPS71334DRCT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS71334DRCT is usually 5 days.
3.What payment methods are accepted for TPS71334DRCT?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS71334DRCT transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS71334DRCT?
TPS71334DRCT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS71334DRCT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS71334DRCT?
For technical support, including TPS71334DRCT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS71334DRCT requirements.
6.How does Aetrix verify that TPS71334DRCT is sourced from the original manufacturer or authorized distributors?
All TPS71334DRCT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS71334DRCT meets industry standards.
7.What is the process for return or replacement of TPS71334DRCT?
All TPS71334DRCT units undergo pre-shipment inspection (PSI). If there is an issue with TPS71334DRCT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS71334DRCT part is unused and in its original packaging.
Return procedure for TPS71334DRCT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TPS71334DRCT Tags
-
MIC5504-1.8YM5-TR
Microchip Technology
-
MIC5504-3.3YM5-TR
Microchip Technology
-
MIC5365-3.0YC5-TR
Microchip Technology
-
MIC5365-1.8YC5-TR
Microchip Technology
-
MIC5365-2.5YC5-TR
Microchip Technology
-
MIC5365-3.3YC5-TR
Microchip Technology
-
MIC5365-3.3YD5-TR
Microchip Technology
-
MIC5317-3.3YM5-TR
Microchip Technology
-
TLV1117LV33DCYR
Texas Instruments
-
MIC5317-3.3YMT-TZ
Microchip Technology
-
MIC5528-3.3YMT-TR
Microchip Technology
-
TLV75801PDRVR
Texas Instruments
Tech Hub
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
LDO regulator guide covering low dropout voltage, power dissipation, thermal design, PSRR, output noise, capacitor stability, adjustable LDO circuits, LDO vs buck converter and datasheet selection chec…
Conditional Access Module guide covering CAM meaning, CI/CI+ interface, smart card authorization, DVB security workflow, TV and set-top box compatibility, internal electronics, ESD protection, connecto…
Guide to electronic component obsolescence covering EOL risk, PCN/PDN notices, last-time buy planning, replacement options, form-fit-function validation, counterfeit risk and BOM lifecycle management.
18650 battery guide covering lithium-ion cell basics, 3.6V/3.7V voltage, 4.2V charging, mAh and Wh capacity, protected cells, chargers, BMS, series-parallel packs, holders, welding and sourcing checks.…
