Texas Instruments TPS720115DRVT

Overview

TPS720115DRVT from Texas Instruments is a 350 mA ultra-low VIN, RF-optimized low-dropout linear regulator with bias pin, delivering 1.15 V output at ±2% accuracy over –40°C to 125°C, 110 mV dropout at full load, and 48 μV_RMS output noise (10 Hz–100 kHz). It operates with dual-rail input (VIN ≥ VOUT + 0.5 V, VBIAS ≥ VOUT + 1.4 V), enabling high-efficiency power architectures in RF-sensitive portable systems.

For engineers reviewing the TPS720115DRVT datasheet, TPS720115DRVT pinout, TPS720115DRVT application, or TPS720115DRVT equivalent, key selection criteria include its bias-supplied light-load regulation capability (IN floating, ≤500 μA), 140 μs startup time with monotonic rise, 80 dB VIN PSRR at 10 kHz, and compatibility with 2.2 μF ceramic output capacitors in space-constrained layouts.

Technical Context

The TPS720115DRVT implements a dual-rail NMOS LDO architecture where VIN supplies the main power path and VBIAS powers the control circuitry independently-enabling VIN as low as VOUT + 0.5 V while maintaining stability and transient performance. Its BIAS pin accepts 2.5 V to 5.5 V and must exceed VOUT by ≥1.4 V for proper operation.

It features built-in soft-start limiting inrush current to 100 mA + I_LOAD, thermal shutdown at 160°C, undervoltage lockout on VBIAS (2.45 V nominal, 150 mV hysteresis), and active-high enable with TTL/CMOS-compatible thresholds (VEN(HI) = 1.1 V, VEN(LO) ≤ 0.4 V).

Key Specifications

Pinout & Package

TPS720115DRVT is packaged in a 2 mm × 2 mm SON-6 (DRV) package with exposed thermal pad, optimized for thermal performance in compact PCB layouts.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LDO regulator applications.

Compared with TPS720115DRVT, TPS72012DRVT offers identical performance at 1.2 V-ideal for design reuse with minor voltage adjustment-while TPS79512DRVR trades dual-rail flexibility and RF-grade noise/PSRR for smaller footprint and lower cost in less demanding applications.

Availability

TPS720115DRVT is available at Aetrix Electronics and suitable for RF transceiver power supply, mobile camera core voltage, low-power microcontroller core rail, and wireless sensor node bias rail applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for TPS720115DRVT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of LDO innovation focused on efficiency, noise, and integration.

The TPS720 family was designed specifically for RF-sensitive, battery-powered portable electronics-delivering ultra-low noise, dual-rail efficiency, and light-load regulation to extend runtime while meeting stringent EMI and signal integrity requirements.

FAQ

What is the minimum required input voltage for TPS720115DRVT to regulate at 1.15 V?

The TPS720115DRVT requires VIN ≥ VOUT + 0.5 V under recommended operating conditions, so minimum VIN is 1.65 V. However, its ultra-low dropout of 110 mV at 350 mA allows stable regulation down to VIN = 1.26 V (1.15 V + 110 mV) when VBIAS is properly biased-enabling tighter system-level voltage margins than conventional LDOs.

Can TPS720115DRVT operate with the IN pin disconnected?

Yes-the TPS720115DRVT supports regulated output with IN floating under light loads (≤500 μA), sourcing current exclusively from the BIAS pin. This feature is explicitly documented and enables power-saving modes where upstream DC-DC converters are disabled while the LDO maintains core rail integrity, as verified in Figure 7 and Section 8.1.2 of the TPS720 datasheet.

What output capacitor value and type are required for stability with TPS720115DRVT?

The TPS720115DRVT is stable with a minimum 2.2 μF ceramic output capacitor (X5R or X7R dielectric recommended). Maximum ESR must be <250 mΩ. No input capacitor is required for stability, though a 0.1–1 μF ceramic cap on IN improves transient response and noise rejection per TI's layout guidance.

How does the BIAS pin function in TPS720115DRVT, and what voltage range is acceptable?

The BIAS pin powers the internal control circuitry independently of VIN, allowing VIN to operate near VOUT for higher efficiency. TPS720115DRVT requires VBIAS ≥ VOUT + 1.4 V (i.e., ≥2.55 V) and ≤5.5 V. Typical operation uses 2.7–3.3 V; exceeding the lower bound ensures proper UVLO release and PSRR performance.

Does TPS720115DRVT include protection features, and what are their thresholds?

Yes-TPS720115DRVT integrates thermal shutdown (trip at 160°C, reset at 140°C), current limiting (420–800 mA depending on conditions), and VBIAS undervoltage lockout (2.45 V nominal, 150 mV hysteresis). These are production-tested features documented in Sections 6.5 and 7.3 of the official datasheet, not optional or application-dependent behaviors.