Texas Instruments TPS73701DRBRG4

Overview

TPS73701DRBRG4 from Texas Instruments is an adjustable-output, 1A low-dropout (LDO) voltage regulator with NMOS pass transistor topology, reverse current protection, and ultra-low dropout voltage of 122 mV typical at 1 A (new silicon). It operates from 2.2 V to 5.5 V input, delivers ±1.5% overall accuracy over line/load/temperature, and stabilizes with only a 1 µF ceramic output capacitor. It is used in point-of-load regulation for FPGAs and microprocessors where low quiescent current and fast transient response are critical.

For engineers reviewing the TPS73701DRBRG4 datasheet, TPS73701DRBRG4 pinout, TPS73701DRBRG4 application, or TPS73701DRBRG4 equivalent, key selection criteria include dropout voltage at full load, shutdown current (<20 nA), thermal performance in DRB package (R_θJA = 49.4°C/W), and compatibility with 1 µF ceramic capacitors for space-constrained portable designs.

Technical Context

The TPS73701DRBRG4 uses an NMOS pass transistor in voltage-follower configuration, enabling reverse current blocking and insensitivity to output capacitor ESR. Its BiCMOS process delivers high precision while maintaining low ground pin current - 880 µA at 1 A load (new silicon) and <20 nA in shutdown.

It features an internal charge pump (~4 MHz) to drive the NMOS gate above V_OUT, supporting ultra-low dropout. The adjustable version relies on FB pin feedback (1.204 V reference) and supports external C_FB up to 0.1 µF to reduce noise and improve load transients - no NR pin is available on TPS73701.

Key Specifications

Pinout & Package

TPS73701DRBRG4 is packaged in an 8-pin VSON (DRB) package, 3 mm × 3 mm, with exposed thermal pad connected to GND. The DRB variant uses a top-view pinout optimized for compact layout and thermal performance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LDO regulator applications.

Compared with TPS73701DRBRG4, TPS7A3701DRBR offers tighter accuracy and higher PSRR at identical footprint, while ADM7172ACPZ-R7 provides double the current and lower noise but requires added components for reverse protection - making TPS73701DRBRG4 optimal for cost-sensitive, space-constrained 1 A portable designs requiring inherent reverse blocking.

Availability

TPS73701DRBRG4 is available at Aetrix Electronics and suitable for point-of-load regulation for FPGAs, post-regulation for switching supplies, and portable battery-powered equipment requiring stable component supply, consistent parametric performance, and long-term lifecycle support.

Supply support for TPS73701DRBRG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, specializing in analog and embedded processing technologies with over 90 years of innovation in power management ICs.

The TPS737 family was designed specifically for portable and battery-operated systems requiring ultra-low dropout, reverse current protection, and minimal external components - targeting FPGA, microprocessor, and ASIC core rail applications.

FAQ

What is the maximum output voltage supported by TPS73701DRBRG4?

The TPS73701DRBRG4 is an adjustable LDO with no fixed output; its output voltage is set externally via resistor divider on the FB pin. The datasheet specifies a range of 1.20 V to 5.5 V, limited by the 5.5 V absolute maximum input voltage and internal 1.204 V reference. For example, using R1 = 39.2 kΩ and R2 = 30.1 kΩ yields 3.3 V output. The TPS73701DRBRG4 must never be operated with V_IN < V_OUT + V_DO (≥122 mV) to avoid dropout failure.

Does TPS73701DRBRG4 require an external noise-reduction capacitor?

No - the TPS73701DRBRG4 does not have an NR (noise reduction) pin. Unlike fixed-output versions of the TPS737 family, the TPS73701DRBRG4 uses the FB pin for feedback and supports a feedback capacitor (C_FB) up to 0.1 µF from FB to OUT to reduce output noise and improve load transient response. This C_FB replaces the function of the NR capacitor in fixed versions, and the TPS73701DRBRG4 achieves 27 × V_OUT µV_RMS noise (10 Hz–100 kHz) with standard 10 µF C_OUT.

What is the thermal performance of TPS73701DRBRG4 in its DRB package?

The TPS73701DRBRG4 in DRB (VSON-8) package has R_θJA = 49.4°C/W (new silicon) and R_θJB = 22.0°C/W when mounted with a 2×2 thermal via array under the exposed GND pad. At 1 A load and 122 mV dropout, power dissipation is 122 mW; with 25°C ambient, junction temperature rises to ~37°C - well within the –40°C to 125°C operating range. Derating is required above 85°C ambient unless additional copper area or airflow is provided.

Can TPS73701DRBRG4 be used with input voltages below 2.2 V?

No - the absolute minimum input voltage for TPS73701DRBRG4 is 2.2 V per the Recommended Operating Conditions table. Operation below this violates specification and may cause improper regulation or damage. For V_OUT = 1.2 V, the minimum valid input is max(2.2 V, V_OUT + V_DO) ≈ 1.322 V, but the 2.2 V floor dominates. Attempting to operate at 2.0 V input risks loss of regulation, increased dropout, and potential instability - the TPS73701DRBRG4 must be powered within 2.2 V to 5.5 V.

How does the enable pin (EN) function on TPS73701DRBRG4?

The EN pin on TPS73701DRBRG4 is active-high with TTL/CMOS-compatible thresholds: V_EN(HIGH) ≥ 1.7 V enables regulation, while V_EN(LOW) ≤ 0.5 V places the device in shutdown mode drawing <20 nA. The pin must never be left floating - if unused, tie directly to IN. During shutdown, the pass transistor gate is fully discharged, ensuring true reverse current blocking and zero output current. Startup time is 431 µs (new silicon) with 1 µF C_OUT and 30 Ω load.