Texas Instruments TPS7A10105PDSER

Overview

TPS7A10105PDSER from Texas Instruments is a 300-mA ultra-low-dropout linear regulator (LDO) with dual-supply architecture (VIN + VBIAS), fixed 1.05-V output, 0.75-V minimum input voltage, 70-mV max dropout at 300 mA (YKA package), and ±1.5% output accuracy over –40°C to +125°C. It powers core rails in space-constrained, battery-powered devices such as smart wearables and camera modules.

For engineers reviewing the TPS7A10105PDSER datasheet, TPS7A10105PDSER pinout, TPS7A10105PDSER application, or TPS7A10105PDSER equivalent, key selection criteria include ultra-low VIN support (down to 0.75 V), bias-rail efficiency optimization (VBIAS = 1.7–5.5 V), active output discharge (P-version), 1.6-µA VIN quiescent current, and WSON-6 (DSE) package compatibility with high-density PCB layouts.

Technical Context

The TPS7A10105PDSER implements a dual-input LDO architecture where VIN supplies the pass element while VBIAS powers internal control circuitry-enabling stable regulation even when VIN is only 70 mV above VOUT. This decoupling allows operation below traditional bandgap thresholds and supports LILO (low-input, low-output) systems.

It integrates global UVLO with independent rising/falling thresholds on both VIN (675 mV / 600 mV) and VBIAS (1.54 V / 1.44 V), thermal shutdown at 160°C, and a P-version–specific 120-Ω active pulldown resistor for monotonic output discharge. PSRR reaches 60 dB at 1 kHz under both VIN and VBIAS excitation.

Key Specifications

Pinout & Package

TPS7A10105PDSER is packaged in a 1.50-mm × 1.50-mm, 6-pin WSON (DSE) package with wettable flanks, optimized for automated optical inspection and thermal performance (R_θJA = 188.8°C/W).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ultra-low-dropout LDO applications.

Compared with TPS7A10105PDSER, TPS7A11105PDSER simplifies supply design but sacrifices ultra-low-VIN operation and bias-rail efficiency, while NCP163AMX105TBG offers smaller footprint and lower cost at the expense of current drive, accuracy, and advanced protection features.

Availability

TPS7A10105PDSER is available at Aetrix Electronics and suitable for smart wearables, camera modules, and portable medical devices requiring stable component supply, long-lifecycle support, and guaranteed traceable sourcing.

Supply support for TPS7A10105PDSER includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog and embedded processing technologies, with leadership in power management ICs and high-reliability signal chain solutions.

The TPS7A10 family is designed for ultra-low-voltage, ultra-low-power applications demanding sub-1-V operation, high accuracy, and minimal quiescent current-targeting next-generation portable and wearable electronics.

FAQ

What is the minimum input voltage supported by the TPS7A10105PDSER?

The TPS7A10105PDSER supports a minimum input voltage (VIN) of 0.75 V, enabled by its dual-supply architecture where VBIAS powers internal circuitry independently. This allows regulation even when VIN is only 70 mV above the 1.05-V output-making it suitable for deeply discharged batteries or post-DC/DC pre-regulated rails. The device remains functional down to 0.75 V as long as VBIAS is within 1.7–5.5 V.

Does the TPS7A10105PDSER include active output discharge functionality?

Yes, the TPS7A10105PDSER (P-version) includes an integrated active output discharge circuit featuring a 120-Ω pulldown resistor activated upon EN deassertion or thermal shutdown. This ensures rapid, controlled discharge of the output capacitor-preventing floating voltages and enabling predictable power sequencing. The discharge time constant is t = 120·R_L·C_OUT/(120 + R_L), where R_L is the parallel load resistance.

What are the recommended input and output capacitors for the TPS7A10105PDSER?

The TPS7A10105PDSER requires a minimum 2.2-µF ceramic input capacitor (C_IN) from IN to GND and a 2.2–22-µF ceramic output capacitor (C_OUT) from OUT to GND. A 0.1-µF ceramic capacitor (C_BIAS) is mandatory from BIAS to GND. All capacitors must be X5R/X7R dielectric with ≤250-mΩ ESR. Placement must be adjacent to respective pins with short, low-inductance traces to ensure stability and transient response.

How does the TPS7A10105PDSER handle undervoltage conditions on VIN and VBIAS?

The TPS7A10105PDSER implements independent global UVLO circuits on both VIN and VBIAS pins, internally ANDed to prevent startup until both rails exceed their thresholds: VIN > 675 mV (rising) / > 600 mV (falling), and VBIAS > 1.54 V (rising) / > 1.44 V (falling). Hysteresis of 75 mV (VIN) and 80 mV (VBIAS) prevents chatter during brownout. If either rail drops below its falling threshold, the LDO disables and discharges VOUT (if P-version).

What is the thermal performance of the TPS7A10105PDSER in its WSON-6 package?

In the 1.50-mm × 1.50-mm WSON-6 (DSE) package, the TPS7A10105PDSER has a junction-to-ambient thermal resistance (R_θJA) of 188.8°C/W under standard JEDEC JESD51-7 conditions. Its junction-to-board (R_θJB) is 101.0°C/W, indicating effective heat transfer to the PCB. Thermal shutdown activates at 160°C (rising) and resets at 145°C (falling), protecting against sustained overload or poor layout.