Texas Instruments TPS7A10105PDSET

Overview

TPS7A10105PDSET from Texas Instruments is a 300-mA, ultra-low-dropout linear regulator with dual-supply architecture (VIN + VBIAS), fixed 1.05-V output, 70-mV max dropout at 300 mA (YKA package), ±1.5% output accuracy over –40°C to +125°C, and 1.6-µA VIN quiescent current. It powers core rails in space-constrained, battery-operated devices such as smart watches and camera modules.

For engineers reviewing the TPS7A10105PDSET datasheet, TPS7A10105PDSET pinout, TPS7A10105PDSET application, or TPS7A10105PDSET equivalent, key selection criteria include ultra-low input voltage support (0.75 V min), BIAS-rail dependency for LILO operation, active output discharge (P-version only), thermal shutdown (160°C), and WSON-6 (DSE) package compatibility with 1.50-mm × 1.50-mm PCB footprints.

Technical Context

The TPS7A10105PDSET implements a dual-rail LDO architecture where VIN supplies the pass element while VBIAS powers internal control circuitry-enabling stable regulation down to 0.5 V output from inputs as low as 0.75 V. Its global UVLO requires both VIN > 675 mV (rising) and VBIAS > 1.54 V (rising) before enabling regulation.

It features built-in monotonic soft-start (525–1200 µs), active output discharge via integrated 120-Ω pulldown (P-version only), and high PSRR (60 dB @ 1 kHz) achieved through low-noise bandgap and high-gain error amplifier design. Output stability requires ≥2.2-µF ceramic COUT with ESR < 250 mΩ.

Key Specifications

Pinout & Package

TPS7A10105PDSET is packaged in a 1.50-mm × 1.50-mm, 6-pin WSON (DSE) package with wettable flanks and exposed thermal pad. The package supports reflow soldering and provides 101.0°C/W junction-to-board thermal resistance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ultra-low-dropout LDO applications.

Compared with XC6210B102MR-G and RT9080L-105GJ6F, the TPS7A10105PDSET uniquely supports 0.75-V inputs via BIAS rail, achieves lowest IQ in class, and integrates active discharge and dual UVLO-making it the only option for true LILO wearable and medical applications demanding guaranteed startup and clean shutdown.

Availability

TPS7A10105PDSET is available at Aetrix Electronics and suitable for smart wearables, camera modules, wireless earbuds, and portable medical sensors requiring stable component supply, long-term lifecycle support, and traceable sourcing for volume production.

Supply support for TPS7A10105PDSET includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog and embedded processing technologies, with leadership in power management ICs and precision analog solutions.

The TPS7A10 family is designed for ultra-low-power, space-constrained battery-operated systems requiring sub-1-V outputs, ultra-low IQ, and dual-supply flexibility - targeting wearables, hearables, and portable medical devices.

FAQ

What is the minimum input voltage required for TPS7A10105PDSET to regulate 1.05 V?

The TPS7A10105PDSET requires VIN ≥ 0.75 V minimum, but actual regulation depends on both VIN and VBIAS. For 1.05-V output, VIN must exceed VOUT + VDO (70 mV max), so ≥1.12 V is needed if using VIN-only mode. With VBIAS ≥1.7 V, VIN can be as low as 0.75 V due to the dual-rail architecture - confirmed in TI SBVS314B datasheet Section 6.3.

Does TPS7A10105PDSET support active output discharge, and how does it work?

Yes, TPS7A10105PDSET (P-version) includes active output discharge: an internal 120-Ω pulldown MOSFET connects OUT to GND when EN is low or thermal shutdown activates. Discharge time depends on COUT and parallel load resistance per τ = 120·RL/(120+RL)·COUT. This feature ensures rapid, predictable VOUT decay - critical for reliable power sequencing in wearables.

What are the recommended input and output capacitors for TPS7A10105PDSET?

TI specifies ≥2.2-µF X7R/X5R ceramic capacitor from IN to GND, ≥0.1-µF ceramic from BIAS to GND, and ≥2.2-µF (up to 22-µF) ceramic from OUT to GND. All capacitors must have ESR < 250 mΩ. Placement must be adjacent to respective pins with short, low-inductance traces - detailed in SBVS314B Sections 8.1 and 10.2.

How does the global UVLO function in TPS7A10105PDSET?

The TPS7A10105PDSET uses two independent UVLO circuits - one on VIN (rising threshold 675 mV) and one on VBIAS (rising threshold 1.54 V) - combined via internal AND logic. Regulation only begins when both rails exceed their thresholds; either rail dropping below its falling threshold (VIN: 600 mV, VBIAS: 1.44 V) disables the LDO. This prevents partial powering and ensures robust startup/shutdown behavior.

Is TPS7A10105PDSET pin-compatible with other TPS7A10 variants?

TPS7A10105PDSET uses the 6-pin WSON (DSE) package and shares identical pinout with all TPS7A10x PDSET variants (e.g., TPS7A1012PDSET, TPS7A1015PDSET). Pin functions (IN, GND, BIAS, OUT, EN, NC) and footprint are identical - allowing drop-in replacement across fixed-output voltages within the same package option.