Texas Instruments TPS84210RKGT
- Part No.:
- TPS84210RKGT
- Manufacturer:
- Texas Instruments
- Package:
- 39-BQFN Exposed Pad
- Datasheet:
-
TPS84210RKGT.pdf
- Description:
- IC REG BUCK ADJ 2A 39B1QFN
- Quantity:
- Payment:

- Shipping:

Inventory:793
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Product details
Overview
TPS84210RKGT from Texas Instruments is a 2-A synchronous buck DC/DC power module integrating MOSFETs, inductor, and passives in a 39-pin BQFN package. It operates from 2.95 V to 6 V input, delivers adjustable output (0.8 V–3.6 V) with ±1% reference accuracy, supports 500 kHz–2 MHz switching frequency, and achieves up to 96% efficiency-designed for FPGA and DSP point-of-load regulation in compact PCI and communications infrastructure.
For engineers reviewing the TPS84210RKGT datasheet, TPS84210RKGT pinout, TPS84210RKGT application, or TPS84210RKGT equivalent, key selection criteria include its integrated thermal performance (12°C/W θJA), programmable UVLO, remote sense capability (SENSE+), power-good signaling (PWRGD), and synchronization support via RT/CLK-critical for timing-critical embedded power systems requiring minimal external components.
Technical Context
The TPS84210RKGT implements a current-mode synchronous buck topology with internal compensation, enabling stable operation with as few as three external components. Its control loop includes an internal 0.8-V reference, adjustable soft-start (SS/TR), and output voltage tracking/sequencing via STSEL configuration.
Thermal management leverages a 11.0 mm × 9.0 mm BQFN PowerPAD (PGND) with 12°C/W junction-to-ambient resistance, supporting full 2-A output at 85°C ambient without airflow. Protection features include overcurrent (3.5-A threshold), thermal shutdown (175°C), and undervoltage lockout with adjustable hysteresis via INH/UVLO.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.95 V to 6 V - supports single 3.3-V or 5-V rail inputs without pre-regulation |
| Output Current | 2 A continuous - rated at 85°C ambient with natural convection cooling |
| Output Voltage Range | 0.8 V to 3.6 V - set via external RSET resistor with ±1% initial accuracy |
| Switching Frequency | 500 kHz to 2 MHz - adjustable via RT/CLK pin or synchronizable to external clock |
| Efficiency | Up to 96% - measured at VIN = 5 V, VOUT = 3.3 V, IOUT = 1 A, fSW = 1.5 MHz |
| Thermal Resistance | 12°C/W θJA - enables high-power density layout on standard 2-layer PCBs |
| Protection Features | OCP (3.5-A limit), thermal shutdown (175°C), UVLO, PWRGD fault signaling |
Pinout & Package
The TPS84210RKGT uses a 39-pin BQFN (RKG) package measuring 11.0 mm × 9.0 mm with exposed thermal pad (PowerPAD, pin 37) connected to PGND. The package supports standard QFN reflow profiles and requires multi-via connection of PGND to PCB power ground for optimal thermal and electrical performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AGND (pins 1,5,29,33,34) | Analog ground reference | Must be externally tied to analog ground plane; separate from PGND except at single-point via under PowerPAD |
| PGND (PowerPAD, pin 37) | Power ground return | Primary thermal and electrical path to PCB ground; requires ≥6 vias to inner ground layers |
| VIN (pins 30,31,32) | Input power supply | Connects to 2.95–6-V source; requires ≥47-µF ceramic input capacitance placed adjacent to pins |
| VOUT (pins 8,9,10,11,12,13,14,38) | Regulated output | Distributes 0.8–3.6-V output; requires ≥47-µF ceramic + bulk capacitance per output voltage range |
| SENSE+ (pin 36) | Remote voltage sensing | Connects directly to load VOUT node to compensate for PCB trace IR drop and improve regulation accuracy |
| VADJ (pin 35) | Output voltage programming | Resistor divider to AGND sets VOUT; open circuit yields 0.8-V default |
| RT/CLK (pin 4) | Frequency control/sync | External resistor sets fSW; external clock signal overrides RT mode for system-level timing alignment |
| PWRGD (pin 27) | Power-good status | Open-drain output asserting low when VOUT deviates >7% (rising) or >9% (falling) from setpoint |
| SS/TR (pin 6) | Soft-start/tracking control | Capacitor sets ramp time; external voltage enables sequencing with other rails |
| STSEL (pin 7) | SS/TR mode select | Tied to AGND enables internal SS (~1.1-ms ramp); floating enables tracking mode |
| INH/UVLO (pin 28) | Inhibit/UVLO adjustment | Open-drain logic input disables regulator; resistor to AGND sets UVLO threshold (e.g., 3.135 V rising) |
Key Features
| Feature | Design Value |
|---|---|
| Integrated power solution | Combines controller, dual MOSFETs, shielded inductor, and compensation in one BQFN-reduces design cycle by eliminating magnetics selection and loop tuning |
| Remote sensing (SENSE+) | Enables <±0.5% load regulation across PCB traces up to 100 mΩ resistance, critical for high-current FPGA core rails |
| Programmable UVLO | Adjustable turn-on threshold via resistor on INH/UVLO pin ensures clean startup in multi-rail systems with brown-out immunity |
| Synchronization capability | RT/CLK pin accepts 500 kHz–2 MHz external clock, enabling noise-sensitive applications (e.g., ADCs, RF) to avoid beat frequencies |
| Output voltage sequencing | SS/TR and STSEL pins support controlled power-up order between core and I/O rails-essential for Xilinx/Intel FPGA compliance |
| EN55022 Class B emissions | Meets conducted and radiated EMI limits without external shielding or ferrites, simplifying EMC certification for industrial equipment |
Applications
| Compact PCI / PXI Express | DSP and FPGA Point-of-Load |
|---|---|
Use Scenario: Powering PCIe add-in cards with tight board space and strict thermal limits. IC Role / Device Role / Timing Role: Primary 1.2-V/1.8-V core regulator delivering 2 A with remote sense to maintain voltage at FPGA die under dynamic load. Use Value: Eliminates discrete buck controller + inductor + MOSFET layout; 12°C/W thermal resistance sustains full load at 85°C ambient without forced air. |
Use Scenario: Supplying configurable logic and memory interfaces in high-density digital signal processing modules. IC Role / Device Role / Timing Role: Dual-rail sequenced supply (VCCINT/VCCIO) using SS/TR and STSEL pins to meet Xilinx Spartan-7 startup timing requirements. Use Value: Adjustable 0.8–3.6-V output range covers 0.85-V AI accelerator cores and 3.3-V transceivers; ±1% reference accuracy ensures timing margin compliance. |
| Broadband Infrastructure | Automated Test Equipment |
Use Scenario: Providing stable 3.3-V/2.5-V rails for RF front-end ICs and data converters in 5G small cells. IC Role / Device Role / Timing Role: Low-noise, synchronized buck converter referenced to system clock to suppress switching artifacts in ADC sampling bands. Use Value: RT/CLK synchronization eliminates heterodyne interference; EN55022 Class B compliance avoids costly EMI filtering in enclosed base station enclosures. |
Use Scenario: Powering mixed-signal test head electronics requiring precise voltage stability during calibration sequences. IC Role / Device Role / Timing Role: Precision 1.8-V supply with SENSE+ feedback ensuring <±10 mV deviation across 0–2-A load steps during parametric testing. Use Value: 93% efficiency at 1.8 V/1 A reduces self-heating drift; PWRGD output validates rail readiness before test pattern execution. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck power module applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS84250RHLR | Higher 5-A output, 4.5–17-V input, larger 10.5-mm × 9.5-mm QFN package | Targets higher-power DSPs and SoCs requiring >3-A rails; not pin-compatible | Select when output current >2 A or input voltage exceeds 6 V is required; requires PCB redesign |
| LMZ31503RRDT | 3-A output, 2.95–6-V input, same 11-mm × 9-mm footprint but 40-pin QFN vs. 39-pin BQFN | Offers integrated LDO post-regulator for ultra-low-noise analog supplies; different pinout and control logic | Choose for mixed-signal systems needing clean 1.2-V analog rails; verify STSEL/SS/TR compatibility with existing firmware |
Compared with TPS84210RKGT, the TPS84250RHLR provides greater current headroom at the cost of size and input range, while the LMZ31503RRDT adds analog-grade regulation but requires layout and control interface adaptation-neither is pin-compatible, making TPS84210RKGT optimal for space-constrained 2-A designs with strict thermal budgets.
Availability
TPS84210RKGT is available at Aetrix Electronics and suitable for compact PCI, FPGA point-of-load, and broadband infrastructure applications requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.
Supply support for TPS84210RKGT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in high-reliability power conversion solutions.
The TPS84210RKGT belongs to TI's SWIFT™ integrated power module family, engineered for rapid deployment in space-constrained, thermally demanding applications such as communications infrastructure and programmable logic systems.
FAQ
What is the maximum output current capability of the TPS84210RKGT under natural convection cooling?
The TPS84210RKGT delivers a continuous 2-A output current at 85°C ambient temperature with natural convection cooling on a standard 100 mm × 100 mm double-sided PCB. This rating is validated per JEDEC JESD51-2A thermal testing and assumes proper PGND via implementation and recommended input/output capacitance.
How does the SENSE+ pin function in the TPS84210RKGT, and where should it be connected?
The SENSE+ pin (pin 36) enables remote voltage sensing to compensate for PCB trace resistance between the TPS84210RKGT output and the load. It must be connected directly to the VOUT net at the load point-not at the module pins-to achieve ±0.5% load regulation. If unused, it must be tied to VOUT at the module.
Can the TPS84210RKGT synchronize its switching frequency to an external clock, and what are the valid frequency and voltage ranges?
Yes, the TPS84210RKGT supports external clock synchronization via the RT/CLK pin (pin 4). Valid synchronization frequencies range from 500 kHz to 2 MHz, with CLK high-level voltage between 2.2 V and 3.3 V, and low-level voltage ≤0.4 V. The device automatically detects CLK mode when an external signal is present.
What is the purpose of the STSEL pin on the TPS84210RKGT, and how does it affect system behavior?
The STSEL pin (pin 7) selects between slow-start (SS) and tracking (TR) modes. When tied to AGND, it enables internal soft-start with ~1.1-ms output ramp time. When left floating, it activates tracking mode, allowing the TPS84210RKGT output to follow an external voltage applied to the SS/TR pin-enabling precise power sequencing with other rails.
Does the TPS84210RKGT require external compensation components, and how many external parts are needed for basic operation?
No, the TPS84210RKGT integrates full loop compensation and does not require external compensation components. For basic operation, only three external parts are needed: an RSET resistor (VADJ to AGND) to set output voltage, an RT resistor (RT/CLK to AGND) to set switching frequency, and a soft-start capacitor (SS/TR to AGND).
TPS84210RKGT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 39-BQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.95V
- Voltage - Input (Max):
- 6V
- Voltage - Output (Min/Fixed):
- 0.8V
- Voltage - Output (Max):
- 3.6V
- Current - Output:
- 2A
- Frequency - Switching:
- 500kHz ~ 2MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 39-B1QFN (11x9)
TPS84210RKGT FAQ
1.How can I place an order for TPS84210RKGT through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS84210RKGT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS84210RKGT reliable?
The price and inventory of TPS84210RKGT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS84210RKGT is usually 5 days.
3.What payment methods are accepted for TPS84210RKGT?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS84210RKGT transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS84210RKGT?
TPS84210RKGT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS84210RKGT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS84210RKGT?
For technical support, including TPS84210RKGT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS84210RKGT requirements.
6.How does Aetrix verify that TPS84210RKGT is sourced from the original manufacturer or authorized distributors?
All TPS84210RKGT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS84210RKGT meets industry standards.
7.What is the process for return or replacement of TPS84210RKGT?
All TPS84210RKGT units undergo pre-shipment inspection (PSI). If there is an issue with TPS84210RKGT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS84210RKGT part is unused and in its original packaging.
Return procedure for TPS84210RKGT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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