Texas Instruments TPS92075D/NOPB
- Part No.:
- TPS92075D/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- LED Drivers
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
TPS92075D/NOPB.pdf
- Description:
- IC LED DRIVER OFFL TRIAC 8SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
TPS92075D/NOPB from Texas Instruments is a non-isolated, phase-dimmable buck PFC LED driver IC with integrated digital phase-angle decoder and analog current reference control. It delivers constant LED current across 50/60 Hz AC inputs, supports leading/trailing-edge TRIAC dimmers, operates from 11–18 VVCC, and features overvoltage protection (18 V), thermal shutdown (160 °C), and 8-pin SOIC packaging.
For engineers reviewing the TPS92075D/NOPB datasheet, TPS92075D/NOPB pinout, TPS92075D/NOPB application, or TPS92075D/NOPB equivalent, this page provides verified technical context, real-world dimming behavior, package-specific thermal metrics, functional alternatives for bulb-replacement and area-lighting designs, and supply-chain support for production ramp-up.
Technical Context
The TPS92075D/NOPB implements a hysteretic, peak-current-controlled, constant off-time architecture to regulate LED current in buck or buck-boost topologies. Its digital controller continuously analyzes ASNS pin timing to derive line frequency (45–65 Hz), conduction angle, and symmetry-enabling dynamic selection between DC reference mode (≤70% conduction) and synchronized triangular ramp mode (>70%) for high power factor and low THD.
It uses dual sensing paths: ASNS for phase detection (1.0 V rising / 0.5 V falling thresholds) and ISNS for cycle-by-cycle current limiting (500 mV typical threshold). Gate drive is optimized with 3–8 Ω sourcing/sinking resistance, and COFF pin sets off-time via external capacitor and pull-down resistor (33–60 Ω), enabling EMI reduction through frequency variation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 11–18 V - powers internal logic and gate driver; UVLO at 6.4 V (falling) ensures stable start-up under deep dimming |
| ISNS Threshold | 500 mV ±55 mV - sets peak inductor current via external sense resistor; enables precise LED current regulation |
| ASNS Thresholds | 0.500 V (falling), 1.000 V (rising) - detects TRIAC conduction angle with 150 µs noise immunity for robust dimmer compatibility |
| Thermal Shutdown | 160 °C with 20 °C hysteresis - halts switching at die temperature limit; resumes at ~140 °C to prevent thermal runaway |
| COFF Off-Time Control | 1.20 V threshold + 33–60 Ω pull-down - determines minimum off-time (280 µs max); enables spread-spectrum EMI reduction |
| GATE Drive Strength | 3–8 Ω sourcing/sinking - drives MOSFET gates directly without external buffers; supports fast turn-on/turn-off transitions |
| Dimmer Compatibility | Leading & trailing-edge TRIAC - includes phase-symmetry balancing algorithm to suppress 100/120 Hz flicker from asymmetric dimmers |
Pinout & Package
TPS92075D/NOPB is housed in an 8-pin SOIC (D) package with exposed pad not present; θJA = 112.3 °C/W under JEDEC high-K board conditions. Pin functions are validated per TI SLUSB88B Rev. January 2014.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| 1 | GND | Power and signal ground reference; connects to PCB ground plane for thermal and noise control |
| 2 | COFF | Off-time timing node; external capacitor and resistor set constant off-time duration and enable EMI spreading |
| 3 | VCC | Bias supply input; powers internal regulator and gate driver; includes OVP (18 V) and UVLO (6.4 V falling) |
| 4 | GATE | MOSFET gate driver output; 3–8 Ω drive strength enables direct connection to power switch in buck/buck-boost stages |
| 5 | ISNS | Current sense input; monitors voltage across external sense resistor to terminate each switching cycle at programmed peak current |
| 6 | NC | No connect - internally unused; must remain unconnected per datasheet |
| 7 | NC | No connect - internally unused; must remain unconnected per datasheet |
| 8 | ASNS | Phase-angle detection input; samples rectified AC waveform to decode TRIAC firing angle and enable dimming control |
Key Features
| Feature | Design Value |
|---|---|
| Digital phase-angle decoder | Processes ASNS timing to distinguish 50/60 Hz line frequency and conduction angle length - enables seamless dimmer interoperability without external microcontroller |
| Phase-symmetry balancing | Adjusts LED current reference line-cycle-by-line-cycle when positive/negative half-cycle conduction differs by >20% - eliminates visible flicker from asymmetric TRIAC dimmers |
| Active hold function | Increases current reference after ASNS fall event in buck topology - suppresses input filter resonance and prevents output flicker during AC zero-crossing dropout |
| Ramp-mode PFC | Generates synchronized triangular reference above 70% conduction angle - achieves >0.9 power factor and low THD without complex analog circuitry |
| Constant off-time control | Uses COFF pin voltage threshold and external RC network - inherently varies switching frequency to ease EMI filtering requirements and reduce BOM cost |
Applications
| Bulb Replacement | Area Lighting |
|---|---|
|
Use Scenario: Retrofit A19 or PAR30 LED lamps into legacy TRIAC-dimmer-controlled residential sockets. IC Role / Device Role / Timing Role: Primary PFC LED driver controlling buck-stage MOSFET; decodes phase angle in real time to maintain smooth dimming down to 5% light output. Use Value: Eliminates need for external hold circuitry while sustaining >90 lm/W efficacy and <5% THD across all dimming levels. |
Use Scenario: Indoor commercial troffer or panel lights requiring flicker-free dimming in office environments with mixed-brand dimmers. IC Role / Device Role / Timing Role: Constant-current controller implementing phase-symmetry balancing and active hold to suppress 100/120 Hz ripple under asymmetric dimmer loads. Use Value: Delivers <0.5% peak-to-peak LED current variation across line cycles - meets IEEE 1789-2015 low-risk flicker requirements. |
| Dimmable LED Lamps | Non-Dimmable LED Lamps |
|
Use Scenario: UL-listed GU10 or E26 LED spotlights deployed in hospitality settings where smooth 1–100% dimming is mandatory. IC Role / Device Role / Timing Role: Digital reference generator adapting between DC and ramp modes based on conduction angle; synchronizes reference to line zero-crossings. Use Value: Achieves <1% dimming resolution and <0.1 s response to dimmer position change - indistinguishable from incandescent fade behavior. |
Use Scenario: Cost-sensitive outdoor wall packs or streetlight modules where dimming is disabled but high PF and reliability are required. IC Role / Device Role / Timing Role: Fixed-reference PFC controller operating in ramp mode only; leverages built-in 50/60 Hz sync and overvoltage protection for robustness. Use Value: Reduces BOM count by 30% vs. two-chip solutions while maintaining >0.95 PF and 125°C junction operation without derating. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LED driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS92074D/NOPB | 6-pin TSOT package; lacks ASNS pin and digital phase decoder - supports only non-dimming, fixed-output configurations | Targeted for cost-optimized, non-dimmable LED lamps where TRIAC compatibility is unnecessary | Select when dimming is disabled and PCB space is constrained; requires separate bias supply design |
| NCL30001DR2G | Analog-based PFC controller with valley-fill input stage; no digital dimming decoder; requires external op-amp for current regulation | Suitable for industrial-grade LED drivers where programmability and flicker suppression are secondary to thermal robustness | Choose for higher ambient temperature operation (150°C ambient rated); adds 4 passive components vs. TPS92075D/NOPB's integrated solution |
Compared with TPS92075D/NOPB, TPS92074D/NOPB reduces system cost and footprint but forfeits dimming capability entirely, while NCL30001DR2G offers superior thermal margin at the expense of higher component count, no digital dimmer intelligence, and no phase-symmetry balancing - making TPS92075D/NOPB the only choice for flicker-critical, TRIAC-compatible consumer lighting.
Availability
TPS92075D/NOPB is available at Aetrix Electronics and suitable for bulb replacement, area lighting, and dimmable LED lamp designs requiring stable component supply, full production traceability, and long-term lifecycle support.
Supply support for TPS92075D/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with over 50 years of innovation in energy-efficient power conversion.
The TPS92075D/NOPB belongs to TI's LED lighting controller product line, engineered specifically for single-stage, phase-dimmable AC/DC LED drivers that eliminate external microcontrollers while meeting ENERGY STAR and IEC 61000-3-2 harmonic standards.
FAQ
What is the primary function of the ASNS pin on the TPS92075D/NOPB?
The ASNS pin on the TPS92075D/NOPB serves as the phase-angle detection input, sampling the rectified AC waveform to determine TRIAC conduction timing. With nominal 1.0 V rising and 0.5 V falling thresholds and 150 µs noise immunity, it enables the TPS92075D/NOPB's digital decoder to compute line frequency, duty cycle, and symmetry - forming the basis for dimming control, ramp-mode activation, and phase-balancing algorithms.
Does the TPS92075D/NOPB support both leading-edge and trailing-edge TRIAC dimmers?
Yes, the TPS92075D/NOPB explicitly supports both leading-edge and trailing-edge TRIAC dimmers, as confirmed in its official features list and application diagrams. Its digital phase decoder adapts to either dimmer type by analyzing ASNS signal edge transitions, and its phase-symmetry balancing algorithm corrects for asymmetry inherent in many trailing-edge implementations - ensuring flicker-free operation across diverse residential and commercial dimmer models.
How does the TPS92075D/NOPB achieve power factor correction without a dedicated PFC stage?
The TPS92075D/NOPB achieves power factor correction through its patented digital reference control architecture: above 70% conduction angle, it generates a line-synchronized triangular current reference that shapes inductor current to closely follow the sinusoidal input voltage. This method delivers >0.9 PF and low THD in a single-stage buck or buck-boost topology - eliminating the need for separate boost-PFC controllers and reducing system cost and size.
What thermal protection mechanisms are built into the TPS92075D/NOPB?
The TPS92075D/NOPB integrates thermal shutdown protection that disables the GATE output when junction temperature reaches 160 °C, with 20 °C hysteresis to prevent oscillation. It also supports external thermal foldback via COFF pin modification using an NTC thermistor - allowing designers to initiate current reduction before reaching the hard shutdown threshold, improving system reliability in enclosed or high-ambient environments.
Can the TPS92075D/NOPB operate without an ASNS signal?
Yes, the TPS92075D/NOPB can operate without an ASNS signal: grounding the ASNS pin configures it for non-dimming mode with a fixed 0.394 V (50/127) reference, enabling use in cost-sensitive, non-dimmable LED lamps. However, this disables phase-symmetry balancing, active hold, ramp-mode PFC, and digital synchronization - resulting in reduced dimmer compatibility and higher THD compared to full-function operation.
TPS92075D/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Bulk
- Product Status:
- Active
- Type:
- AC DC Offline Switcher
- Topology:
- Step-Down (Buck), Step-Up (Boost)
- Internal Switch(s):
- No
- Number of Outputs:
- 1
- Voltage - Supply (Min):
- 11V
- Voltage - Supply (Max):
- 18V
- Voltage - Output:
- -
- Current - Output / Channel:
- -
- Frequency:
- -
- Dimming:
- Triac
- Applications:
- Lighting
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
TPS92075D/NOPB FAQ
1.How can I place an order for TPS92075D/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS92075D/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS92075D/NOPB reliable?
The price and inventory of TPS92075D/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS92075D/NOPB is usually 5 days.
3.What payment methods are accepted for TPS92075D/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS92075D/NOPB transactions.
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4.How is shipping managed for TPS92075D/NOPB?
TPS92075D/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS92075D/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS92075D/NOPB?
For technical support, including TPS92075D/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS92075D/NOPB requirements.
6.How does Aetrix verify that TPS92075D/NOPB is sourced from the original manufacturer or authorized distributors?
All TPS92075D/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS92075D/NOPB meets industry standards.
7.What is the process for return or replacement of TPS92075D/NOPB?
All TPS92075D/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with TPS92075D/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS92075D/NOPB part is unused and in its original packaging.
Return procedure for TPS92075D/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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