Texas Instruments TPS92310DGSR/NOPB

Overview

TPS92310DGSR/NOPB from Texas Instruments is an off-line primary-side sensing LED controller for isolated and non-isolated flyback topologies, delivering 350 mA LED current with adaptive constant-on-time (COT) or peak-current-mode (PCM) control, inherent power factor correction (PFC), and quasi-resonant valley switching. It operates from 85–132 V_AC, supports CRM mode, and integrates over-temperature, over-voltage, and cycle-by-cycle current limiting for solid-state lighting drivers.

For engineers reviewing the TPS92310DGSR/NOPB datasheet, TPS92310DGSR/NOPB pinout, TPS92310DGSR/NOPB application, or TPS92310DGSR/NOPB equivalent, key selection criteria include its VSSOP-10 package, 10-pin primary-side sensing architecture, programmable delay timing via RDLY, dual-mode operation (COT/PCM), and integrated ZCD-based valley switching for EMI reduction and efficiency optimization in AC-input LED lamp designs.

Technical Context

The TPS92310DGSR/NOPB implements critical-conduction-mode (CRM) control using zero-crossing detection (ZCD) on the auxiliary winding to enable valley-switching, minimizing switching loss and EMI. Its adaptive ON-time algorithm dynamically adjusts t_ON based on primary inductor peak current and secondary discharge time, enabling inherent PFC without external compensation.

Operating modes-COT for high power factor or PCM for lower output current ripple-are selected via MODE1/MODE2 pins. Protection functions include over-temperature shutdown at 165°C, output OVP triggered after three consecutive ZCD-PEAK > 4.3 V cycles, and dual-threshold over-current detection (0.64 V for non-isolated, 3.4 V for isolated topologies).

Key Specifications

Pinout & Package

TPS92310DGSR/NOPB uses a 10-pin VSSOP (Very Small Outline Package) with 0.5 mm pitch and exposed thermal pad. The package supports surface-mount assembly and provides thermal dissipation capability of θ_JA = 120°C/W under standard JEDEC conditions.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LED controller applications.

Compared with UCC28810DR and NCP1015ST100T3G, the TPS92310DGSR/NOPB uniquely combines programmable valley-switching delay, dual-mode topology support (isolated/non-isolated), and primary-side regulation-enabling fewer external components, higher efficiency, and direct compliance with IEC 61000-3-2 without added circuitry.

Availability

TPS92310DGSR/NOPB is available at Aetrix Electronics and suitable for LED lamp retrofitting, commercial troffer drivers, PAR30/38 lighting modules, and GU10 directional spotlights requiring stable component supply, long-lifecycle support, and consistent parametric performance across production batches.

Supply support for TPS92310DGSR/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, specializing in analog, embedded processing, and power management technologies with broad industrial and automotive qualification.

The TPS92310DGSR/NOPB belongs to TI's LED lighting controller product line, engineered specifically for high-efficiency, low-BOM-count AC/DC LED drivers with inherent PFC and primary-side regulation-targeting cost-sensitive, thermally constrained lamp and fixture applications.

FAQ

What is the recommended minimum VCC bypass capacitance for stable operation of the TPS92310DGSR/NOPB?

The TPS92310DGSR/NOPB requires a minimum 10 µF ceramic or tantalum capacitor connected between the VCC pin and PGND/AGND. This value ensures sufficient energy storage during transient load steps and stabilizes the internal bias rail during startup and fault recovery. Lower values may cause erratic gate drive or premature UVLO dropout under dynamic LED load conditions. Always place the capacitor within 5 mm of the VCC and PGND pins.

How does the TPS92310DGSR/NOPB achieve power factor correction without an external PFC controller?

The TPS92310DGSR/NOPB achieves inherent power factor correction through adaptive constant-on-time (COT) control in critical conduction mode (CRM). By synchronizing MOSFET turn-on to transformer demagnetization (via ZCD) and modulating t_ON based on instantaneous line voltage, it shapes input current to closely follow the sinusoidal AC waveform-achieving >0.9 PF without auxiliary boost stages or complex digital algorithms. This behavior is confirmed in the datasheet's typical application waveforms and design example.

Can the TPS92310DGSR/NOPB operate in non-isolated buck-derived topologies?

Yes, the TPS92310DGSR/NOPB supports non-isolated operation in buck-derived configurations, but only in Constant On-Time (COT) mode-selected by pulling MODE2 to GND and leaving MODE1 open. In this configuration, the ISNS OCP threshold defaults to 0.64 V, and ZCD functionality is disabled. The device retains all protections (OVP, OCP, thermal shutdown), making it suitable for low-cost, single-stage LED drivers where galvanic isolation is not required.

What is the maximum allowable delay time (tDLY) between ZCD trigger and GATE turn-on in the TPS92310DGSR/NOPB?

The TPS92310DGSR/NOPB does not specify an absolute maximum tDLY, but practical limits derive from CRM timing constraints: tDLY must be less than the off-time (t_OFF) to avoid missing the next valley. With t_OFF-MAX = 94 µs and typical tDLY values ranging 200–500 ns (per Figure 18), exceeding ~1 µs risks forcing operation into discontinuous conduction mode (DCM), degrading PFC and increasing current ripple. Designers should optimize RDLY using Equation (3) and verify with oscilloscope measurements of VSW and GATE edges.

Does the TPS92310DGSR/NOPB require external compensation components on the COMP pin?

Yes, the TPS92310DGSR/NOPB requires an external RC network on the COMP pin to stabilize the LED current regulation loop. A typical design uses a 2.2 µF capacitor from COMP to AGND, optionally with a series resistor for phase margin tuning. The COMP pin sources 27 µA internally, so the network must be sized to maintain loop bandwidth below 10 Hz for effective PFC-confirmed in the "Compensation Capacitor Selection" section of the datasheet and validated in the design example.