Diodes Incorporated TRAC020LHQ36

Overview

TRAC020LHQ36 from Fast Analog Solutions is a 20-cell Field-Programmable Analog Device (FPAD) in QSOP-36 package, implementing reconfigurable analog functions including NIP, NEGATE, ADD, LOG, ALOG, RECTIFY, and AUX via 3-bit per-cell serial programming. It operates from ±2V/3V dual supplies, delivers 12MHz small-signal bandwidth (NIP mode), <1.2mV input offset, and 80dB dynamic range for real-time analog computation and signal conditioning. Used in sonar front-ends and transducer linearization.

For engineers reviewing the TRAC020LHQ36 datasheet, TRAC020LHQ36 pinout, TRAC020LHQ36 application, or TRAC020LHQ36 equivalent, key selection criteria include programmable cell function mapping, dual-rail supply tolerance (VDD=+3V, VSS=−2V), 10MHz max clock frequency for configuration, and industrial temperature range (−40°C to +85°C) support for embedded instrumentation.

Technical Context

The TRAC020LHQ36 implements a top-down computational analog design methodology using 20 independent cells, each configurable via 3-bit serial instruction to perform one of eight functions (e.g., NIP, ADD, LOG). Each cell features rail-to-rail input range (VSS+1.0V to VDD−2.0V), 60MΩ input resistance (NIP), and programmable gain accuracy within ±0.4% (NIP), ±1.0% (ADD).

Configuration occurs via synchronous serial interface (DATA, CLOCK, RESET, PD, CLCR, DOUT) with positive-edge clocking and daisy-chain capability. Logic-level I/O (DOUT, CLCR, RESET, PD, CLOCK) operates at 5V logic swing (VOH=4.0V, VOL=0.4V), while analog cells operate independently on ±2V/3V supplies with 2.5mA typical IDD and −2.5mA ISS quiescent current.

Key Specifications

Pinout & Package

TRAC020LHQ36 uses a 36-pin QSOP package with 0.635mm pitch, 11.9mm × 4.9mm body, and exposed pad not electrically connected. Pin 1 marked by notch; pin numbering counterclockwise from top-left corner.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar field-programmable analog function applications.

Compared with TRAC010LHQ28 and TRAC020LHQ44, the TRAC020LHQ36 uniquely balances cell density, QSOP footprint, and analog I/O count for mid-complexity embedded signal conditioning - making it optimal for space-constrained industrial controllers where 20-cell flexibility is required but TSSOP assembly is prohibitive.

Availability

TRAC020LHQ36 is available at Aetrix Electronics and suitable for ultrasonic sensing, analog correlation engines, transducer linearization, and real-time control loop compensation requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for TRAC020LHQ36 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Fast Analog Solutions Ltd., a Zetex Group company based in Oldham, UK, specializes in programmable analog ICs enabling rapid hardware iteration without custom silicon.

The TRAC® family was designed to replace discrete op-amp networks in analog computation, control, and signal conditioning - delivering FPGA-like reconfigurability with analog-domain precision and nanosecond latency.

FAQ

What is the minimum configuration time to load a full 20-cell program?

A full 60-bit configuration requires 60 clock cycles. With maximum 10MHz CLOCK frequency, this takes 6.0µs. Including RESET assertion (≥100ns) and post-load stabilization (<1µs), total setup time is ≤7.2µs - verified in Figure 14 settling waveforms under VDD=3.0V, VSS=−2.0V conditions.

Can TRAC020LHQ36 operate with a single 5V supply?

No. The device requires dual asymmetric supplies: VDD = +3.0V ±0.15V and VSS = −2.0V ±0.10V. This creates a 5V total rail span but mandates separate positive and negative regulators. Single-supply operation violates Absolute Maximum Ratings (voltage on any pin ≤7.0V relative to VSS), risking latch-up or permanent damage.

How is analog signal integrity maintained during cell reconfiguration?

During programming, analog signal paths remain active unless PD is asserted. Configuration occurs in background via shift registers; cell function changes take effect only after RESET release. Figure 14 shows <1µs settling after cell switching (e.g., NIP→NEG), confirming no signal disruption during live operation - critical for continuous ultrasonic monitoring.

What is the thermal drift behavior of the LOG function across temperature?

The LOG cell exhibits ±0.4% gain error from −40°C to +85°C (Figure 12), with output voltage shift <±70mV over full range (Figure 11). This stability arises from matched diode pairs and on-chip temperature compensation - enabling accurate logarithmic compression in wide-temperature sonar receivers without external calibration.