Texas Instruments TS3DV642RUARQ1
- Part No.:
- TS3DV642RUARQ1
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 42-WFQFN Exposed Pad
- Datasheet:
-
TS3DV642RUARQ1.pdf
- Description:
- IC MUX/DEMUX 12 X 1:2 42WQFN
- Quantity:
- Payment:

- Shipping:

Inventory:5,724
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TS3DV642RUARQ1 from Texas Instruments is an automotive-qualified, bidirectional 12-channel (6 differential) analog multiplexer/demultiplexer optimized for HDMI 2.0, DisplayPort 1.4 HBR2, MIPI DPHY/CPHY, and LVDS interfaces up to 6 Gbps. It operates from a single 3.3 V supply, delivers –1.6 dB insertion loss at 3.0 GHz, –17 dB return loss at 3.0 GHz, and –3-dB differential bandwidth of 5.8 GHz, enabling high-fidelity signal routing in ADAS camera and infotainment video paths.
For engineers reviewing the TS3DV642RUARQ1 datasheet, TS3DV642RUARQ1 pinout, TS3DV642RUARQ1 application, or TS3DV642RUARQ1 equivalent, this page provides verified electrical specifications, validated automotive-grade thermal performance (–40°C to 105°C), confirmed WQFN-42 wettable flank package mapping, and real-world HDMI/MIPI switching use cases with jitter and eye diagram impact data.
Technical Context
The TS3DV642RUARQ1 implements a passive FET-based switch architecture with integrated charge-pump drive, enabling low on-resistance (6.5–12 Ω) and flatness (<2.0 Ω) across 0–3.6 V common-mode range. Its functional modes-enabled via EN, SEL1, and SEL2-support discrete 1:2 or 2:1 channel selection, full-port A/B enablement, or Hi-Z power-down (6 μA).
It handles bidirectional differential signals with CMV 0–3.6 V and single-ended CMOS up to 5.5 V, while maintaining inter-pair skew ≤10 ps and intra-pair skew ≤8 ps at 1.7 GHz. IOFF protection ensures no back-powering when VCC = 0 V, critical for hot-swap automotive display systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data Rate | 6 Gbps - supports HDMI 2.0 main-link and DP 1.4 HBR2 without retiming |
| Differential BW | 5.8 GHz - preserves signal integrity through 3rd harmonic of 6-Gbps NRZ |
| Insertion Loss | –1.6 dB at 3.0 GHz - minimizes amplitude degradation in high-speed video links |
| Return Loss | –17 dB at 3.0 GHz - ensures <10% reflected energy at critical video frequencies |
| On-Resistance | 6.5–12 Ω - enables <0.5% voltage drop across typical 50-Ω terminated channels |
| Power Consumption | 45 μA active / 6 μA standby - reduces thermal load in space-constrained head units |
| ESD Rating | 3 kV HBM / 1 kV CDM - meets automotive board-level ESD robustness requirements |
Pinout & Package
TS3DV642RUARQ1 is housed in a 42-pin WQFN package (3.5 mm × 9.0 mm, 0.5 mm pitch) with wettable flanks for automated optical inspection and enhanced solder joint reliability in automotive reflow profiles.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC (Pin 1) | Power Supply | Single 3.3 V supply input; decoupling required per TI layout guidelines |
| EN (Pin 2) | Enable Control | Active-high global enable; drives all channels Hi-Z when low |
| D0+ / D0– (Pins 5/6) | Common Port, Ch0 | Bidirectional differential I/O; connects to source/sink main-link lanes |
| D0+A / D0–A (Pins 38/37) | Port A, Ch0 | 1:2 demux output or 2:1 mux input for DisplayPort/HDMI path A |
| D0+B / D0–B (Pins 29/28) | Port B, Ch0 | 1:2 demux output or 2:1 mux input for alternate video path (e.g., rear-seat display) |
| SCL_A / SDA_A (Pins 42/41) | Port A DDC | I²C-compatible DDC clock/data for HDMI/DP AUX channel on Port A |
| HPD_A (Pin 19) | Port A Hot Plug Detect | Open-drain HPD signaling for sink detection on Port A |
| SEL1 / SEL2 (Pins 16/17) | Channel Select | Binary-encoded control for discrete 1:2 routing or full-port A/B selection |
Key Features
| Feature | Design Value |
|---|---|
| Automotive Q100 Grade 2 | Qualified for –40°C to +105°C operation per AEC-Q100 Rev G, enabling use in instrument clusters and ADAS ECUs |
| IOFF Protection | Prevents current leakage into powered-off rails when VCC = 0 V, eliminating risk of back-powering downstream SoCs |
| Wettable Flank WQFN | Enables automated AOI of solder joints on bottom-side pins, improving manufacturing yield in automotive PCB assembly |
| Low Inter-Pair Skew | ≤10 ps skew between differential lanes ensures timing alignment for HDMI 2.0 4K60 and DP 1.4 UHD video |
| DDC/HPD/CEC Support | Full auxiliary channel routing (SCL/SDA/HPD/CEC) on both ports enables seamless HDMI handshaking across switched displays |
Applications
| ADAS Camera Switching | HDMI 2.0 Head Unit Mux |
|---|---|
Use Scenario: Routing dual MIPI CSI-2 camera streams (front/rear) to a single image signal processor in an ADAS domain controller. IC Role / Device Role / Timing Role: Bidirectional 2:1 multiplexer selecting between two 4-lane MIPI DPHY camera modules operating at 4.5 Gbps per lane. Use Value: Enables hardware-level camera arbitration without retimers; maintains <17 ps added jitter at 3.4 Gbps per lane as measured on TI evaluation boards. | Use Scenario: Switching HDMI 2.0 video output between internal SoC and external HDMI connector in automotive infotainment head units. IC Role / Device Role / Timing Role: 1:2 demultiplexer directing main-link, DDC, HPD, and CEC signals to either front-display or rear-seat entertainment system. Use Value: Preserves HDMI 2.0 eye mask compliance at 6.0 Gbps with only 20 ps added total jitter on Port A, verified per HDMI specification test points. |
| DisplayPort 2:1 Selection | MIPI CPHY CSI-2 Trio Switching |
Use Scenario: Selecting between two DisplayPort sources (e.g., CPU and media box) feeding a single DP scaler in digital cockpit displays. IC Role / Device Role / Timing Role: 2:1 multiplexer handling DP HBR2 (5.4 Gbps) main-link lanes, AUX, and HPD on both paths with matched trace lengths. Use Value: Achieves –16 dB off-isolation at 3.0 GHz, preventing crosstalk-induced bit errors during source switching events. | Use Scenario: Arbitrating three CPHY trios (T0/T1/T2) from dual camera modules to a single CPHY receiver in next-gen automotive vision systems. IC Role / Device Role / Timing Role: Channel-flexible 6-differential switch assigning arbitrary pins to CPHY trio groups, supporting 3.5 Gbps per trio. Use Value: Leverages functional equivalence of all six differential channels-no fixed lane mapping required-simplifying PCB layout and firmware configuration. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed analog mux applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TS3DV642RUKRQ1 | Same silicon die, 20-pin WQFN (2.5 mm × 4.5 mm); 6-channel only, no DDC/HPD/CEC support | Limited to pure data-lane switching (e.g., LVDS or basic MIPI DSI); unsuitable for HDMI/DP with auxiliary channels | Select when board space is constrained and auxiliary signaling is handled externally. |
| TMUXHS4212RTWR | 4-channel, 12-Gbps rated; higher bandwidth but no automotive qualification or IOFF protection | Targeted at industrial/commercial high-speed serial links; not validated for AEC-Q100 Grade 2 temperature or vibration stress | Choose only for non-automotive designs requiring >6 Gbps margin or lower insertion loss at 6 GHz. |
Compared with TS3DV642RUARQ1, TS3DV642RUKRQ1 sacrifices auxiliary channel routing and package size for footprint reduction, while TMUXHS4212RTWR trades automotive qualification and fail-safe IOFF for higher raw bandwidth-neither offers drop-in replacement capability due to pin count, signal routing, or qualification mismatch.
Availability
TS3DV642RUARQ1 is available at Aetrix Electronics and suitable for automotive infotainment systems, ADAS camera domain controllers, and digital cockpit display subsystems requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for TS3DV642RUARQ1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company specializing in analog and embedded processing technologies, with leadership in automotive, industrial, and personal electronics markets.
The TS3DV642RUARQ1 belongs to TI's automotive-qualified high-speed analog switch portfolio, designed specifically for video signal routing in safety-critical and thermally demanding vehicle environments including head units, surround-view systems, and HUD controllers.
FAQ
What is the maximum data rate supported by the TS3DV642RUARQ1?
The TS3DV642RUARQ1 supports up to 6 Gbps per differential channel, validated for HDMI 2.0, DisplayPort 1.4 HBR2, and MIPI DPHY at 4.5 Gbps. Its 5.8 GHz –3-dB bandwidth and –1.6 dB insertion loss at 3.0 GHz ensure compliance with eye mask and jitter budgets for these standards. The TS3DV642RUARQ1 datasheet specifies 6.0 Gbps as the maximum data rate under recommended operating conditions.
Does the TS3DV642RUARQ1 require separate power supplies for analog and digital sections?
No, the TS3DV642RUARQ1 uses a single 3.3 V supply (VCC, Pin 1) for both analog signal path and digital control logic. It supports 1.8 V, 3.3 V, or 5.0 V logic levels on SEL1, SEL2, and EN inputs, but the core switch operation depends solely on the 3.3 V rail. This simplifies power design in automotive head units where only one low-noise 3.3 V rail is typically available. The TS3DV642RUARQ1 does not have separate AVDD/DVDD pins.
How does the TS3DV642RUARQ1 handle hot-plug detection (HPD) signals in HDMI applications?
TS3DV642RUARQ1 routes HPD signals bi-directionally on dedicated pins (HPD, HPD_A, HPD_B) with open-drain output structure compatible with HDMI specification. When used in 1:2 demux mode, HPD from the source passes through to either Port A or Port B based on SEL1/SEL2 state, enabling correct sink detection and EDID handshake. The TS3DV642RUARQ1 does not buffer or level-shift HPD-it preserves native 0–5 V signaling integrity across all three HPD paths.
Is the TS3DV642RUARQ1 pin-compatible with other members of the TS3DV642-Q1 family?
No, TS3DV642RUARQ1 is not pin-compatible with other variants such as TS3DV642RUKRQ1 (20-pin WQFN) or TS3DV642ZQNRQ1 (32-pin VQFN). The RUARQ1 variant uses a 42-pin WQFN package with unique pinout supporting full DDC, HPD, and CEC routing on both ports. Pin mapping differs significantly across package options, and migration requires PCB redesign. Always verify package-specific pin functions in the TS3DV642RUARQ1 datasheet before substitution.
What thermal performance can be expected from the TS3DV642RUARQ1 in a typical automotive PCB layout?
In standard 4-layer automotive PCBs with 2 oz copper and thermal vias to inner ground planes, the TS3DV642RUARQ1 exhibits a junction-to-board thermal resistance (RθJB) of 9.7 °C/W. At 45 μA active current and 3.3 V supply, power dissipation remains below 0.15 mW-resulting in negligible temperature rise (<0.1°C) above ambient. This allows placement near heat-sensitive image sensors or display drivers without thermal derating. The TS3DV642RUARQ1 thermal metrics are fully characterized per JEDEC JESD51 standards.
TS3DV642RUARQ1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 42-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Multiplexer/Demultiplexer
- Circuit:
- 12 x 1:2
- Independent Circuits:
- 1
- Current - Output High, Low:
- -
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 105°C
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount, Wettable Flank
- Supplier Device Package:
- 42-WQFN (3.5x9)
TS3DV642RUARQ1 FAQ
1.How can I place an order for TS3DV642RUARQ1 through Aetrix?
Please submit a Request for Quotation (RFQ) for TS3DV642RUARQ1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TS3DV642RUARQ1 reliable?
The price and inventory of TS3DV642RUARQ1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TS3DV642RUARQ1 is usually 5 days.
3.What payment methods are accepted for TS3DV642RUARQ1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TS3DV642RUARQ1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TS3DV642RUARQ1?
TS3DV642RUARQ1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TS3DV642RUARQ1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TS3DV642RUARQ1?
For technical support, including TS3DV642RUARQ1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TS3DV642RUARQ1 requirements.
6.How does Aetrix verify that TS3DV642RUARQ1 is sourced from the original manufacturer or authorized distributors?
All TS3DV642RUARQ1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TS3DV642RUARQ1 meets industry standards.
7.What is the process for return or replacement of TS3DV642RUARQ1?
All TS3DV642RUARQ1 units undergo pre-shipment inspection (PSI). If there is an issue with TS3DV642RUARQ1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TS3DV642RUARQ1 part is unused and in its original packaging.
Return procedure for TS3DV642RUARQ1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TS3DV642RUARQ1 Tags
-
SN74HC138DR
Texas Instruments

-
TC7SB3157CFU,LF(CT
Toshiba Semiconductor and Storage

-
74CBTLV3257PW,118
Nexperia USA Inc.
-
SN74CBTLV3257PWR
Texas Instruments

-
74CBTLV3257GUX
Nexperia USA Inc.

-
74HC154BQ,118
Nexperia USA Inc.

-
P3S0200GMX
NXP USA Inc.

-
SN74CB3Q3245PWR
Texas Instruments
-
SN74CB3Q3257RGYR
Texas Instruments

-
TCA9543APWR
Texas Instruments
-
TCA9546APWR
Texas Instruments

-
SN74HC138N
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
