Texas Instruments TS5N118PWG4
- Part No.:
- TS5N118PWG4
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 16-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
TS5N118PWG4.pdf
- Description:
- IC MUX/DEMUX 1 X 8:1 16TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:4,856
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TS5N118PWG4 from Texas Instruments is a 1-of-8 FET multiplexer/demultiplexer bus switch optimized for high-bandwidth digital and analog signal routing. It features 3 Ω typical ON-state resistance (ron), 25 MHz bandwidth, bidirectional rail-to-rail switching (0–10 V), and operates from 4.75 V to 5.25 V VCC - enabling low-distortion, near-zero-propagation-delay data path control in PCI and memory-interleaving systems.
For engineers reviewing the TS5N118PWG4 datasheet, TS5N118PWG4 pinout, TS5N118PWG4 application, or TS5N118PWG4 equivalent, key selection criteria include its TSSOP-16 package, Ioff partial-power-down capability, 20 pF max OFF-state I/O capacitance (B port), and OE-controlled high-impedance isolation - critical for bus isolation and hot-swap compatibility in networking and computing backplanes.
Technical Context
The TS5N118PWG4 implements an 8-channel FET-based analog/digital switch architecture with integrated charge pump to maintain flat ron across 0–10 V signal swing. Its select inputs (S0–S2) decode one of eight B-port channels to the A port under active-low OE control, supporting true bidirectional data flow without direction pins.
It employs Ioff circuitry to block reverse current during partial power-down, ensuring isolation when VCC = 0 V. The device meets JESD 78 Class II latch-up immunity (>100 mA) and JESD 22 ESD ratings (2000-V HBM, 1000-V CDM), making it suitable for mixed-signal environments requiring robust signal integrity and system-level fault tolerance.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 4.75 V to 5.25 V - ensures stable operation within standard 5-V TTL/PCI supply rails. |
| ron (Typ) | 3 Ω at VCC = 5 V, IO = ±50 mA - enables minimal voltage drop and signal attenuation in high-speed data paths. |
| Bandwidth | 25 MHz - supports baseband video, PCI, and memory-bus signaling without significant gain roll-off. |
| Cio(OFF) | 20 pF max (B port) - reduces capacitive loading on inactive channels to preserve signal edge integrity. |
| VI/O Range | 0 V to 10 V - allows rail-to-rail analog/digital signal switching without level translation. |
| tpd | 0.1 ns - near-instantaneous propagation delay due to FET-switch topology and low ron–Cio product. |
| OISO @ 25 MHz | –50 dB - provides strong channel-to-channel isolation during multi-channel demux operation. |
| Ioff Support | Yes - prevents damaging backflow current when powered down, enabling safe hot-insertion in modular systems. |
Pinout & Package
TSSOP-16 (PW) package: 4.4 mm × 5.0 mm body, 0.65 mm pitch, 1.2 mm max height, JEDEC MO-153 compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (A) | Common I/O port | Bidirectional data terminal connected to selected Bx channel when OE = L. |
| 2 (OE) | Output enable | Active-low control: OE = L enables switching; OE = H forces A–B isolation (high-Z). |
| 3 (S0) | Select input | LSB of 3-bit binary address selecting B1–B8; tied to GND/VCC if unused. |
| 4 (S1) | Select input | Middle bit of 3-bit select code; determines channel mapping per function table. |
| 5 (S2) | Select input | MSB of 3-bit select code; fully defines which B port connects to A. |
| 6–13 (B1–B8) | Input/output ports | Eight independent bidirectional channels; only one connected to A at any time. |
| 14 (VCC) | Power supply | 5-V supply input; powers internal charge pump and logic; requires local decoupling. |
| 15 (GND) | Ground reference | Signal and power return; must be low-inductance connection for noise-sensitive applications. |
| 16 (NC) | No connect | No internal connection; must remain unconnected per datasheet (not tied to GND/VCC). |
Key Features
| Feature | Design Value |
|---|---|
| Charge-pump gate drive | Enables flat 3 Ω ron across full 0–10 V signal range without external biasing. |
| Bidirectional zero-delay switching | Eliminates direction-control logic and enables transparent analog/digital signal pass-through. |
| Ioff partial-power-down protection | Blocks reverse current flow when VCC = 0 V, preventing damage during live insertion or sequencing faults. |
| Low 20 pF OFF-state I/O capacitance | Minimizes crosstalk and signal distortion on unselected B-port lines in dense PCB layouts. |
| PCI interface compliance | Meets timing, voltage, and noise immunity requirements for peripheral component interconnect systems. |
Applications
| PCI Bus Multiplexing | Memory Interleaving Interface |
|---|---|
Use Scenario: Routing multiple PCI add-in cards to a shared host bridge while maintaining signal integrity and timing compliance. IC Role / Device Role / Timing Role: 1-of-8 demultiplexer that selects one card's AD bus to the host under S0–S2 address control, with OE enabling dynamic arbitration. Use Value: 0.1 ns tpd and 25 MHz bandwidth preserve PCI-33 timing margins; 3 Ω ron avoids signal reflection and overshoot on 50-Ω traces. | Use Scenario: Switching between two interleaved DRAM banks in high-throughput embedded controllers to double effective memory bandwidth. IC Role / Device Role / Timing Role: Bidirectional analog switch connecting CPU data bus to either Bank A or Bank B based on address LSBs, synchronized with OE strobe. Use Value: Rail-to-rail 0–10 V support handles DDR I/O voltage swings; Ioff prevents leakage-induced data corruption during bank transition. |
| High-Speed Analog Signal Gating | Hot-Swappable Backplane Isolation |
Use Scenario: Enabling/disabling analog sensor signals (e.g., video, audio) in test equipment without introducing DC offset or harmonic distortion. IC Role / Device Role / Timing Role: Low-distortion signal gate placed between sensor output and ADC input, controlled by microcontroller GPIO via OE. Use Value: 3 Ω ron and 20 pF Cio(OFF) ensure <0.01% THD and >60 dB channel rejection at 10 MHz - critical for 12-bit+ measurement accuracy. | Use Scenario: Isolating failed or unpowered modules in telecom line cards while maintaining backplane continuity for active units. IC Role / Device Role / Timing Role: High-impedance barrier inserted between module data lanes and midplane, activated by supervisor logic upon fault detection. Use Value: Ioff and OE-controlled high-Z state prevent backfeeding into powered-down modules; –50 dB OFF isolation suppresses cross-talk in 10-Gbps serial lanes. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 1-of-8 analog/digital multiplexer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74CBT3244PWR | 8-bit FET bus switch (non-multiplexing); no S0–S2 decoding; fixed A→B path per channel. | Suitable for parallel bus isolation but lacks 1-of-8 channel selection logic. | Choose when bidirectional isolation of 8 independent lines is needed without address decoding. |
| CD74HC4051M96 | CMOS analog multiplexer; 3–15 V VCC range; higher ron (80 Ω typ); no Ioff or charge pump. | Supports wider voltage rails but lacks PCI-speed performance and power-down safety. | Choose for low-cost, wide-VCC general-purpose mux where 25 MHz bandwidth and hot-swap are not required. |
Compared with SN74CBT3244PWR and CD74HC4051M96, the TS5N118PWG4 uniquely combines address-decoded 1-of-8 switching, sub-1-ns propagation delay, and Ioff-enabled safe power sequencing - making it the only option among the three qualified for PCI-compliant, hot-pluggable, high-fidelity signal routing.
Availability
TS5N118PWG4 is available at Aetrix Electronics and suitable for PCI interface design, memory interleaving systems, and high-speed analog gating applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for TS5N118PWG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and connectivity technologies with over 50 years of innovation in high-reliability IC design.
The TS5N118PWG4 belongs to TI's high-bandwidth bus switch product line, engineered specifically for low-distortion, rail-to-rail signal routing in PCI, networking, and data-intensive computing infrastructure.
FAQ
What is the maximum signal voltage range supported by the TS5N118PWG4?
The TS5N118PWG4 supports a 0 V to 10 V data I/O voltage range (VI/O), enabling rail-to-rail analog and digital signal switching without level translation. This specification is validated across the full operating temperature range (–40°C to 85°C) and applies to both A and B ports when the device is enabled (OE = L). Exceeding 10 V may violate absolute maximum ratings and risk permanent damage.
Does the TS5N118PWG4 require external components for proper operation?
The TS5N118PWG4 requires a 0.1 µF ceramic decoupling capacitor between VCC and GND, placed as close as possible to pins 14 and 15. Additionally, OE should be pulled up to VCC via a resistor (value determined by driver sink capability) to ensure high-impedance state during power-up/power-down. No external charge pump or bias circuitry is needed - the internal charge pump is self-contained and fully integrated.
How does the Ioff feature of the TS5N118PWG4 protect system-level designs?
The Ioff feature in the TS5N118PWG4 disables all switch paths and blocks reverse current flow when VCC = 0 V, preventing damaging backfeed from live signal lines into a powered-down subsystem. This enables safe hot-swap capability in modular backplanes and protects downstream logic from latch-up or voltage contention - a requirement verified per JESD 78 Class II (exceeding 100 mA fault current immunity).
Can the TS5N118PWG4 be used in bidirectional analog applications such as audio routing?
Yes, the TS5N118PWG4 supports true bidirectional analog signal routing with near-zero propagation delay and low distortion. Its 3 Ω ron, 20 pF Cio(OFF), and flat frequency response up to 25 MHz make it suitable for line-level audio, video sync, and sensor signal multiplexing. However, for AC-coupled audio paths, DC biasing must ensure signals remain within the 0–10 V VI/O range to avoid clipping or turn-on of internal ESD diodes.
What is the thermal performance of the TS5N118PWG4 in TSSOP-16 (PW) package?
The TS5N118PWG4 in TSSOP-16 (PW) package has a junction-to-ambient thermal resistance (θJA) of 108°C/W under standard JEDEC PCB mounting conditions. At maximum continuous I/O current (±100 mA) and worst-case ron (7.5 Ω), power dissipation remains below 80 mW - resulting in negligible junction temperature rise (<9°C above ambient) in typical applications, eliminating need for heatsinking or airflow.
TS5N118PWG4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 16-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Type:
- Multiplexer/Demultiplexer
- Circuit:
- 1 x 8:1
- Independent Circuits:
- 1
- Current - Output High, Low:
- -
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 4.75V ~ 5.25V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-TSSOP
TS5N118PWG4 FAQ
1.How can I place an order for TS5N118PWG4 through Aetrix?
Please submit a Request for Quotation (RFQ) for TS5N118PWG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TS5N118PWG4 reliable?
The price and inventory of TS5N118PWG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TS5N118PWG4 is usually 5 days.
3.What payment methods are accepted for TS5N118PWG4?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TS5N118PWG4 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TS5N118PWG4?
TS5N118PWG4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TS5N118PWG4 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TS5N118PWG4?
For technical support, including TS5N118PWG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TS5N118PWG4 requirements.
6.How does Aetrix verify that TS5N118PWG4 is sourced from the original manufacturer or authorized distributors?
All TS5N118PWG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TS5N118PWG4 meets industry standards.
7.What is the process for return or replacement of TS5N118PWG4?
All TS5N118PWG4 units undergo pre-shipment inspection (PSI). If there is an issue with TS5N118PWG4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TS5N118PWG4 part is unused and in its original packaging.
Return procedure for TS5N118PWG4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TS5N118PWG4 Tags
-
SN74HC138DR
Texas Instruments

-
TC7SB3157CFU,LF(CT
Toshiba Semiconductor and Storage

-
74CBTLV3257PW,118
Nexperia USA Inc.
-
SN74CBTLV3257PWR
Texas Instruments

-
74CBTLV3257GUX
Nexperia USA Inc.

-
74HC154BQ,118
Nexperia USA Inc.

-
P3S0200GMX
NXP USA Inc.

-
SN74CB3Q3245PWR
Texas Instruments
-
SN74CB3Q3257RGYR
Texas Instruments

-
TCA9543APWR
Texas Instruments
-
TCA9546APWR
Texas Instruments

-
SN74HC138N
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
