STMicroelectronics TS613IDT
- Part No.:
- TS613IDT
- Manufacturer:
- STMicroelectronics
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
TS613IDT.pdf
- Description:
- IC VOLTAGE FEEDBACK 2 CIRC 8SO
- Quantity:
- Payment:

- Shipping:

Inventory:4,064
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Product details
Overview
TS613IDT from STMicroelectronics is a dual wideband operational amplifier designed for high-fidelity upstream line driving in ADSL remote terminals. It delivers 160mA output current into 25Ω, achieves 130MHz gain-bandwidth product, and maintains ultra-low intermodulation distortion (–77dBc IM2/IM3) at 100kHz with ±6V supply - enabling simultaneous multi-carrier amplification in DSL transceivers.
For engineers reviewing the TS613IDT datasheet, TS613IDT pinout, TS613IDT application, or TS613IDT equivalent, key selection criteria include its 40V/µs slew rate, 3nV/√Hz input voltage noise, 200mA short-circuit current capability, and SO8 Exposed-Pad thermal performance - all critical for stable broadband line driver design under 135kHz ADSL upstream bandwidth constraints.
Technical Context
The TS613IDT integrates two independent high-output-current op-amps in a single SO8 Exposed-Pad package, each capable of sourcing/sinking ±200mA with rail-to-rail output swing into 25Ω loads. Its internal compensation supports stable closed-loop gains from +2 to +11 at 25Ω, with phase margins of 60° (AVCL = 14dB) and 40° (AVCL = 6dB) under 15pF capacitive loading.
It operates from ±2.5V to ±6V supplies, features common-mode input range extending to (VCC+) –1V, and uses an electrically isolated exposed thermal pad connected to –VCC on PCB for enhanced thermal dissipation (Rthjc = 16°C/W). Channel separation exceeds –40dB at 1MHz, ensuring minimal crosstalk in differential line driver configurations.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Gain-Bandwidth Product | 130 MHz - enables stable unity-gain-buffered or high-gain (>10×) configurations up to ~10MHz with 25Ω load. |
| Slew Rate | 40 V/µs - supports clean 100kHz+ multi-tone signals without slewing-induced harmonic distortion in ADSL upstream paths. |
| Output Current (min) | 160 mA into 25Ω - sufficient to drive transformer-coupled 100Ω twisted-pair lines at 12.4Vpp required by ADSL over POTS. |
| Input Voltage Noise | 3 nV/√Hz @ 100kHz - preserves SNR in low-level analog signal chains preceding DAC output filtering. |
| Intermodulation Distortion | –77 dBc (2nd & 3rd order) - meets stringent linearity requirements for multi-carrier upstream transmission without spectral regrowth. |
| Supply Voltage Range | ±2.5V to ±6V - compatible with dual-rail ADSL line card supplies and single +12V biasing via mid-rail generation. |
| Thermal Resistance (Junction-to-Case) | 16 °C/W (Exposed-Pad) - allows sustained 2W power dissipation at ambient, critical for continuous upstream transmission. |
Pinout & Package
TS613IDT is housed in an SO8 Exposed-Pad plastic micropackage (order code DW), featuring an electrically isolated thermal pad on the underside connected to –VCC for PCB heat sinking. The exposed pad improves thermal performance without electrical connection to pins.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Non-Inverting Input (Ch1) | High-impedance input node for Ch1; CMVR extends to (VCC+) –1V for flexible biasing in single-supply setups. |
| 2 | Inverting Input (Ch1) | Feedback node for Ch1; input bias current ≤15µA enables high-Z feedback networks without offset drift. |
| 3 | Output (Ch1) | Capable of ±200mA sink/source into 25Ω; requires series 12.5Ω resistors for 100Ω line impedance matching. |
| 4 | VCC– | Negative supply rail; thermal pad must be soldered to –VCC copper pour for optimal Rthjc = 16°C/W. |
| 5 | VCC+ | Positive supply rail; decoupling capacitor (100nF + 1µF) required near pin for high-frequency stability. |
| 6 | Non-Inverting Input (Ch2) | Independent Ch2 input; identical specs to Pin 1 - enables true differential drive without external coupling. |
| 7 | Inverting Input (Ch2) | Independent Ch2 feedback node; supports active impedance matching topologies per ST application note AN2097. |
| 8 | Output (Ch2) | Differential complement to Pin 3; used with Pin 3 to generate 18Vpp differential output across 100Ω line. |
Key Features
| Feature | Design Value |
|---|---|
| Dual high-output-current amplifiers | Each channel delivers ≥160mA into 25Ω load at ±6V - eliminates need for external current boosters in ADSL line drivers. |
| Ultra-low intermodulation distortion | –77dBc IM2/IM3 at 100kHz with 2-tone test - ensures compliance with ITU-T G.992.1 upstream spectral mask without post-filtering. |
| Optimized thermal architecture | Exposed thermal pad with Rthjc = 16°C/W - sustains 2W continuous dissipation during full-rate upstream transmission. |
| Wide supply range & rail-compatible inputs | Operates from ±2.5V to ±6V; input common-mode range includes (VCC+) –1V - simplifies mid-rail biasing in +12V single-supply designs. |
| Stable 25Ω drive capability | Phase margin ≥60° at AVCL = 14dB with 25Ω//15pF load - guarantees robust transient response in transformer-coupled line interfaces. |
Applications
| ADSL Remote Terminal Upstream Driver | DSLAM Line Card Test Signal Generator |
|---|---|
|
Use Scenario: Driving twisted-pair telephone lines in consumer ADSL modems with +12V single supply and passive 1:2 transformer impedance matching. IC Role / Device Role / Timing Role: Dual-channel line driver providing differential 12.4Vpp upstream signal (135kHz BW) while rejecting common-mode noise from POTS band. Use Value: Eliminates discrete transistor output stages; achieves required line level with <360mW total power consumption per channel. |
Use Scenario: Generating calibrated multi-tone test waveforms for ADSL line qualification in lab and production test environments. IC Role / Device Role / Timing Role: Precision wideband signal source delivering spectrally pure 70/80kHz and 180/280kHz tone pairs with <–77dBc spurious content. Use Value: Replaces RF signal generators for basic line characterization; enables low-cost, repeatable intermodulation testing without spectrum analyzer dependency. |
| ISDN-based xDSL Transceiver | High-Speed Data Over Legacy Copper |
|
Use Scenario: Enabling ADSL over ISDN infrastructure requiring upstream bandwidth up to 276kHz with improved SNR over POTS. IC Role / Device Role / Timing Role: High-slew-rate buffer stage after Sallen-Key LPF, preserving edge integrity of multi-carrier symbols up to 276kHz. Use Value: Maintains >65dB THD at 276kHz due to 40V/µs slew rate and 130MHz GBW - avoids symbol corruption in higher-order QAM constellations. |
Use Scenario: Retrofitting legacy telephony infrastructure for Ethernet-over-copper (EoC) or proprietary high-speed data links up to 10Mbps. IC Role / Device Role / Timing Role: Robust analog front-end driver handling variable line impedances (75–120Ω) via active impedance matching network. Use Value: Supports k-factor tunable matching (k = 1.3–1.7) to maintain >–70dB return loss across 100kHz bandwidth without custom transformers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-output-current, low-distortion op-amp applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| THS3091DR | Single-channel, 210MHz GBW, 3000V/µs slew rate, but only 120mA output into 25Ω; no exposed-pad package. | Limited to single-ended or half-differential use; lacks dual-channel integration for space-constrained ADSL RT designs. | Choose when extreme slew rate dominates over channel count and thermal management needs. |
| LMH6629MA/NOPB | Single-channel, 1.5GHz GBW, 3.2nV/√Hz noise, but rated only for 100mA into 100Ω; no 25Ω guaranteed drive spec. | Requires external current boosting for ADSL line levels; higher quiescent current (12.5mA vs. 11mA) reduces efficiency. | Prefer for RF IF amplification where bandwidth >500MHz is essential, not for regulated 25Ω line driving. |
Compared with THS3091DR and LMH6629MA/NOPB, TS613IDT uniquely combines dual-channel integration, 25Ω load certification, exposed-pad thermal performance, and –77dBc intermodulation - making it the only drop-in solution for compact, thermally constrained ADSL upstream line cards.
Availability
TS613IDT is available at Aetrix Electronics and suitable for ADSL remote terminal designs, DSLAM line card test instrumentation, and ISDN-based xDSL transceivers requiring stable component supply with long-lifecycle support.
Supply support for TS613IDT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in analog, power, and automotive ICs with strong heritage in industrial and communications solutions.
The TS613 belongs to ST's high-performance line driver product line, engineered specifically for broadband access equipment requiring high linearity, thermal resilience, and dual-channel integration in space-constrained DSL hardware.
FAQ
Can TS613IDT operate from a single +12V supply?
Yes - the TS613IDT supports single-supply operation using mid-rail biasing. With +12V applied to VCC+ and GND to VCC–, the inputs and outputs function correctly when biased at +6V (e.g., via 47kΩ resistor divider). Its input common-mode range extends to (VCC+) –1V, and output swing reaches within 0.5V of rails into 25Ω, enabling full 12.4Vpp differential line drive.
What is the purpose of the exposed thermal pad on TS613IDT?
The exposed pad is electrically isolated from all pins and must be soldered to a –VCC copper pour on the PCB. It provides a low-thermal-resistance path (Rthjc = 16°C/W) from die to board, allowing safe dissipation of up to 2W continuously. This is essential for maintaining junction temperature below 150°C during sustained upstream transmission at full line level.
How does TS613IDT achieve –77dBc intermodulation distortion?
This performance results from optimized internal transistor sizing, matched differential pairs, and careful layout to minimize nonlinearities. Measured with two 70/80kHz tones at 8Vpp output into 25Ω//15pF, the device achieves –77dBc for both 2nd and 3rd order products - verified per ST's AN2097 application note and confirmed in production test across –40°C to +85°C.
Is TS613IDT pin-compatible with other SO8 dual op-amps?
No - TS613IDT follows a non-standard pinout: Pin 4 = VCC–, Pin 5 = VCC+, and outputs are on Pins 3 and 8 (not Pins 1 and 7). Standard SO8 dual op-amps like LM358 or TL082 use different assignments. Layout redesign is required; however, its footprint matches ST's TS612 and TS614 families for mechanical compatibility.
TS613IDT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Amplifier Type:
- Voltage Feedback
- Number of Circuits:
- 2
- Output Type:
- -
- Slew Rate:
- 40V/µs
- Gain Bandwidth Product:
- 130 MHz
- -3db Bandwidth:
- -
- Current - Input Bias:
- 5 µA
- Voltage - Input Offset:
- 1 mV
- Current - Supply:
- 11mA
- Current - Output / Channel:
- 320 mA
- Voltage - Supply Span (Min):
- 5 V
- Voltage - Supply Span (Max):
- 12 V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SO
TS613IDT FAQ
1.How can I place an order for TS613IDT through Aetrix?
Please submit a Request for Quotation (RFQ) for TS613IDT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TS613IDT reliable?
The price and inventory of TS613IDT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TS613IDT is usually 5 days.
3.What payment methods are accepted for TS613IDT?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TS613IDT transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TS613IDT?
TS613IDT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TS613IDT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TS613IDT?
For technical support, including TS613IDT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TS613IDT requirements.
6.How does Aetrix verify that TS613IDT is sourced from the original manufacturer or authorized distributors?
All TS613IDT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TS613IDT meets industry standards.
7.What is the process for return or replacement of TS613IDT?
All TS613IDT units undergo pre-shipment inspection (PSI). If there is an issue with TS613IDT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TS613IDT part is unused and in its original packaging.
Return procedure for TS613IDT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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