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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

NXP Semiconductors TSA5059ATS/C1,118

Name: TSA5059ATS/C1,118
Brand: NXP Semiconductors
SKU: TSA5059ATS/C1,118
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: TSA5059ATS/C1,118

Manufacturer:: NXP Semiconductors

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 16-LSSOP (0.173", 4.40mm Width)

Datasheet:: TSA5059ATS/C1,118.pdf

Description:: IC PLL FREQ SYNTH 16SSOP

Quantity:: RFQ Add To RFQ list

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Product details

Overview

TSA5059ATS/C1,118 from NXP Semiconductors (formerly Philips) is a 2.7 GHz I²C-bus controlled PLL frequency synthesizer optimized for low phase noise in satellite zero-IF tuning systems. It integrates a 17-bit main divider, selectable divide-by-two prescaler, on-chip crystal oscillator, 5-level ADC, and four programmable I/O ports. It operates from 900 MHz to 2.7 GHz RF input, supports 4–16 MHz crystals, and delivers ≤−157 dBc/Hz phase noise at 250 kHz offset.

For engineers reviewing the TSA5059ATS/C1,118 datasheet, TSA5059ATS/C1,118 pinout, TSA5059ATS/C1,118 application, or TSA5059ATS/C1,118 equivalent, key selection criteria include its 2.7 GHz max RF input with prescaler enable, I²C address select via pin AS, XT/COMP output switching between f_xtal and f_comp, four charge pump current options (100–1540 µA), and compatibility with 3.3 V/5 V microcontrollers.

Technical Context

The TSA5059ATS/C1,118 implements a high-speed PLL architecture with an integrated RF preamplifier driving a 17-bit programmable divider. Its fast phase detector enables high comparison frequencies up to 2 MHz, directly supporting low phase noise performance in satellite tuners. The prescaler-by-two is software-selectable via bit PE and required for operation above 2.3 GHz.

Control is fully I²C-based (standard/fast mode), with four configurable slave addresses set by voltage on pin AS. The IC provides dual reference routing: either the crystal oscillator output (f_xtal) or the divided comparison frequency (f_comp) can be routed to the XT/COMP pin, enabling cascaded synthesizer configurations without external clock sources.

Key Specifications

Parameter	Value and Actual Design Meaning
RF Input Frequency	900–2700 MHz; covers full satellite zero-IF band (950–2150 MHz) and extends to 2.7 GHz with prescaler enabled
Crystal Frequency Range	4–16 MHz; supports standard 4 MHz crystals and higher-frequency variants for improved phase noise
Comparison Frequency	12.5 kHz–2 MHz; 16 selectable ratios (2–320) allow trade-off between step size and loop stability
Charge Pump Current	100/280/600/1230 µA (typ); four programmable levels directly impact loop filter design and lock time
I²C Address Options	4 unique addresses via pin AS voltage; enables multi-synthesizer systems on shared bus without address conflict
Phase Noise (at 250 kHz)	≤−157 dBc/Hz (typ); measured with f_comp = 250 kHz, C1=C0=1; critical for adjacent-channel rejection in DVB-S receivers
Supply Voltage	4.75–5.25 V; compatible with standard 5 V logic rails and tolerant of ±5% regulation
Operating Temperature	−20 °C to +85 °C; qualified for industrial-grade satellite receiver front-end environments

Pinout & Package

SSOP16 package (SOT369-1): plastic shrink small outline, 16 leads, body width 4.4 mm, thermal resistance R_th(j-a) = 144 K/W.

Pin/Terminal	Circuit Role	Design Meaning
CP (1)	Charge pump output	Drives external loop filter; requires connection to base of external NPN transistor for VCO tuning voltage generation
XTAL (2)	Crystal oscillator input	Accepts 4–16 MHz quartz crystal or 2–20 MHz external reference; internal oscillator supports series-resonant crystals
XT/COMP (3)	Configurable reference output	Software-selectable output of f_xtal or f_comp; used to drive second synthesizer or demodulator clock, reducing BOM count
AS (4)	I²C address selection	Voltage-programmed input (0–0.1V_CC, open, 0.4–0.6V_CC, 0.9–V_CC) sets one of four I²C slave addresses
SDA (5)	I²C serial data I/O	Open-drain bidirectional line; compatible with 3.3 V and 5 V I²C buses; supports fast-mode (400 kHz)
SCL (6)	I²C serial clock input	Input-only clock line; level-tolerant to 3.3 V/5 V; synchronizes all register writes and status reads
P3–P0 (7–10)	Programmable I/O ports	Four general-purpose ports; P1–P3 support input/output, P0 supports input/output plus test mode (½f_DIV output)
ADC (11)	Analog-to-digital converter input	3-bit 5-level ADC (0–0.15V_CC to 0.6–V_CC); used for AFC voltage monitoring over I²C
VCC (12)	Power supply	4.75–5.25 V supply; powers all internal blocks including RF preamp, divider chain, and I²C interface
RFA/RFB (13–14)	Differential RF inputs	Asymmetrical drive inputs for 900–2700 MHz RF signal; designed for direct connection to LNB IF outputs
GND (15)	Ground reference	Primary analog/digital ground return; must be connected to low-impedance ground plane near RF section
DRIVE (16)	External NPN transistor driver	Output for base drive of external NPN; emitter grounded, collector drives VCO tuning line through loop filter

Key Features

Feature	Design Value
2.7 GHz RF input capability	Enables single-chip coverage of full Ku-band satellite downlink (10.7–12.75 GHz after LNB mixing) without external prescalers
Selectably enabled divide-by-two prescaler	Bit PE control allows seamless transition between 2.3 GHz (prescaler off) and 2.7 GHz (prescaler on) operation modes
XT/COMP output switching	Reduces system component count by eliminating need for separate reference clock generator when cascading multiple synthesizers
Four programmable charge pump currents	Permits optimization of loop dynamics-low current for narrow bandwidth/low noise, high current for fast lock in set-top box channel zapping
Integrated 5-level ADC on pin ADC	Provides closed-loop automatic frequency control feedback path using only one analog input, simplifying tuner alignment
I²C fast-mode (400 kHz) support	Enables rapid frequency reprogramming during channel changes, meeting <50 ms DVB-S tuning requirements

Applications

Satellite Zero-IF Tuner	Digital Set-Top Box Front-End
Use Scenario: Direct-conversion LNB interface in DVB-S receivers, where IF output (950–2150 MHz) is applied to RFA/RFB pins. IC Role / Device Role / Timing Role: PLL frequency synthesizer generating precise local oscillator signal for downconversion; XT/COMP output feeds demodulator clock. Use Value: Achieves −157 dBc/Hz phase noise at 250 kHz offset, ensuring >45 dB adjacent-channel rejection per ETSI EN 300 429.	Use Scenario: Multi-standard (DVB-S/S2) set-top box requiring fast, low-noise LO synthesis across wide frequency range. IC Role / Device Role / Timing Role: Core frequency synthesis engine; I²C-controlled main divider and reference divider configure step size and loop bandwidth dynamically. Use Value: Four charge pump current settings allow real-time trade-off between lock time (<100 ms) and phase noise during channel change sequences.
Cascaded Synthesizer System	Professional Satellite Receiver
Use Scenario: Dual-tuner architecture using one crystal source shared between two TSA5059A devices via XT/COMP output. IC Role / Device Role / Timing Role: Master synthesizer routes f_xtal to XT/COMP; slave device uses that signal as reference input on XTAL pin. Use Value: Eliminates second crystal, reduces cost and board space, and ensures synchronous reference timing across tuners.	Use Scenario: High-reliability professional receiver operating continuously in headend or broadcast monitoring applications. IC Role / Device Role / Timing Role: Precision LO generator with POR flag and in-lock detection (FL bit) for system health monitoring over I²C. Use Value: Built-in lock detection and power-on reset flag enable autonomous fault recovery and remote diagnostics without host MCU intervention.

Satellite Zero-IF Tuner

Digital Set-Top Box Front-End

Use Scenario: Direct-conversion LNB interface in DVB-S receivers, where IF output (950–2150 MHz) is applied to RFA/RFB pins.

IC Role / Device Role / Timing Role: PLL frequency synthesizer generating precise local oscillator signal for downconversion; XT/COMP output feeds demodulator clock.

Use Value: Achieves −157 dBc/Hz phase noise at 250 kHz offset, ensuring >45 dB adjacent-channel rejection per ETSI EN 300 429.

Use Scenario: Multi-standard (DVB-S/S2) set-top box requiring fast, low-noise LO synthesis across wide frequency range.

IC Role / Device Role / Timing Role: Core frequency synthesis engine; I²C-controlled main divider and reference divider configure step size and loop bandwidth dynamically.

Use Value: Four charge pump current settings allow real-time trade-off between lock time (<100 ms) and phase noise during channel change sequences.

Cascaded Synthesizer System

Professional Satellite Receiver

Use Scenario: Dual-tuner architecture using one crystal source shared between two TSA5059A devices via XT/COMP output.

IC Role / Device Role / Timing Role: Master synthesizer routes f_xtal to XT/COMP; slave device uses that signal as reference input on XTAL pin.

Use Value: Eliminates second crystal, reduces cost and board space, and ensures synchronous reference timing across tuners.

Use Scenario: High-reliability professional receiver operating continuously in headend or broadcast monitoring applications.

IC Role / Device Role / Timing Role: Precision LO generator with POR flag and in-lock detection (FL bit) for system health monitoring over I²C.

Use Value: Built-in lock detection and power-on reset flag enable autonomous fault recovery and remote diagnostics without host MCU intervention.

Equivalent & Alternatives

The following parts are listed as comparable options for similar frequency synthesizer applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
MAX2870ETJ+T	Wider RF range (23.5–6000 MHz), integrated VCO, no external NPN required; lacks ADC and XT/COMP output routing	Better suited for broadband test equipment; less optimal for cost-sensitive satellite tuners requiring crystal reuse	Select MAX2870ETJ+T when integrated VCO and wider frequency coverage outweigh need for cascaded reference routing
ADF4351BCPZ	Includes integrated VCO (137.5–4400 MHz), fractional-N capability, SPI interface; higher power (125 mA vs 37 mA typ)	Preferred for wideband SDR and spectrum analyzer designs; not pin-compatible and requires different loop filter topology	Select ADF4351BCPZ when fractional-N synthesis and self-contained VCO simplify layout, accepting higher power and SPI dependency

Compared with MAX2870ETJ+T and ADF4351BCPZ, the TSA5059ATS/C1,118 offers lower system-level BOM cost in satellite tuners via XT/COMP cascading and integrated 5-level ADC, while trading off VCO integration and fractional-N flexibility for proven zero-IF phase noise performance and I²C simplicity.

Availability

TSA5059ATS/C1,118 is available at Aetrix Electronics and suitable for satellite zero-IF tuners, digital set-top boxes, professional broadcast receivers, and cascaded synthesizer systems requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for TSA5059ATS/C1,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and consumer applications. Formerly Philips Semiconductors, it maintains deep expertise in RF and mixed-signal ICs.

The TSA5059A product line was designed specifically for high-performance satellite TV tuning systems, emphasizing low phase noise, I²C configurability, and system-level integration features like XT/COMP routing and on-chip ADC to reduce external component count.

FAQ

What is the maximum RF input frequency supported by the TSA5059ATS/C1,118?

The TSA5059ATS/C1,118 supports RF input frequencies up to 2.7 GHz when the divide-by-two prescaler is enabled (bit PE = 1). Without the prescaler, the maximum is 2.3 GHz. This dual-range capability allows full coverage of satellite zero-IF bands (950–2150 MHz) and extension into higher Ku-band segments, making the TSA5059ATS/C1,118 suitable for next-generation DVB-S2X tuners requiring extended frequency agility.

How does the XT/COMP pin function in the TSA5059ATS/C1,118?

The XT/COMP pin on the TSA5059ATS/C1,118 is a software-configurable output that can deliver either the crystal oscillator frequency (f_xtal) or the comparison frequency (f_comp), selected via bits XCE and XCS in the I²C control register. When enabled, it eliminates the need for a second crystal in multi-synthesizer systems-for example, one TSA5059ATS/C1,118 acts as master (outputting f_xtal), while another uses that signal as its XTAL reference. This feature directly reduces BOM cost and improves timing coherence across channels.

What are the I²C address configuration options for the TSA5059ATS/C1,118?

The TSA5059ATS/C1,118 provides four programmable I²C slave addresses determined by the voltage applied to pin AS: 0–0.1V_CC (address 0x50), open-circuit (0x51), 0.4–0.6V_CC (0x52), and 0.9–V_CC (0x53). This allows up to four TSA5059ATS/C1,118 devices to coexist on the same I²C bus without address conflict-critical for dual-tuner or quad-output professional satellite receivers. Each address is latched at power-on reset and remains stable until next power cycle.

Does the TSA5059ATS/C1,118 include an analog-to-digital converter, and how is it used?

Yes, the TSA5059ATS/C1,118 integrates a 3-bit, 5-level ADC accessible via pin ADC. Input voltage ranges map to digital codes: 0–0.15V_CC = 000, 0.15–0.3V_CC = 001, 0.3–0.45V_CC = 010, 0.45–0.6V_CC = 011, and 0.6–V_CC = 100. The ADC result is read back in the status byte during I²C READ operations and is commonly used for automatic frequency control (AFC) feedback in satellite tuners, enabling closed-loop correction of VCO drift without external ADC components.

What external components are required for basic loop filter implementation with the TSA5059ATS/C1,118?

The TSA5059ATS/C1,118 requires an external NPN transistor (e.g., BC847) connected to pin DRIVE, with its emitter grounded and collector driving the VCO tuning line. A loop filter-typically a passive PI network-is placed between pin CP (charge pump output) and the transistor's collector. Component values depend on desired loop bandwidth (e.g., 10 kHz), VCO gain (e.g., 100 MHz/V), and selected charge pump current. Philips' SIMPATA software is recommended for simulation. No external op-amp or active filter is needed-the TSA5059ATS/C1,118's on-chip loop amplifier and charge pump provide complete analog control path functionality.

TSA5059ATS/C1,118 Specifications

Product attributes: Attribute value

Manufacturer:: NXP Semiconductors

Series:: -

Package/Case:: 16-LSSOP (0.173", 4.40mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Programmable:: Not Verified

Type:: PLL Frequency Synthesizer

PLL:: No

Input:: Clock, Crystal

Output:: Clock, Crystal

Number of Circuits:: 1

Ratio - Input:Output:: 3:2

Differential - Input:Output:: No/No

Frequency - Max:: 2.7GHz

Divider/Multiplier:: Yes/No

Voltage - Supply:: 4.75V ~ 5.25V

Operating Temperature:: -20°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 16-SSOP

TSA5059ATS/C1,118 FAQ

1.How can I place an order for TSA5059ATS/C1,118 through Aetrix?

Please submit a Request for Quotation (RFQ) for TSA5059ATS/C1,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for TSA5059ATS/C1,118 reliable?

The price and inventory of TSA5059ATS/C1,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TSA5059ATS/C1,118 is usually 5 days.

3.What payment methods are accepted for TSA5059ATS/C1,118?

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TSA5059ATS/C1,118 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your TSA5059ATS/C1,118 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for TSA5059ATS/C1,118?

For technical support, including TSA5059ATS/C1,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TSA5059ATS/C1,118 requirements.

6.How does Aetrix verify that TSA5059ATS/C1,118 is sourced from the original manufacturer or authorized distributors?

All TSA5059ATS/C1,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TSA5059ATS/C1,118 meets industry standards.

7.What is the process for return or replacement of TSA5059ATS/C1,118?

All TSA5059ATS/C1,118 units undergo pre-shipment inspection (PSI). If there is an issue with TSA5059ATS/C1,118, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The TSA5059ATS/C1,118 part is unused and in its original packaging.

Return procedure for TSA5059ATS/C1,118:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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