Texas Instruments TSB43AB21AIPDT

Overview

TSB43AB21AIPDT from Texas Instruments is a single-port 1394a-2000 OHCI-compliant PHY/link-layer controller IC for PCI host systems, supporting S100/S200/S400 data rates (100/200/400 Mbits/s), integrated 49.152-MHz LLC clock generation, and IEEE 1394a power-down modes for battery operation. It implements full PCI bus mastering with cacheline burst transfers up to 132 MB/s and deep FIFO buffering to absorb PCI latency.

For engineers reviewing the TSB43AB21AIPDT datasheet, TSB43AB21AIPDT pinout, TSB43AB21AIPDT application, or TSB43AB21AIPDT equivalent, key selection criteria include OHCI register compatibility, 1394a arbitration enhancements, SBP-2 optimized physical write posting, DV/MPEG timestamp hardware acceleration, and D0–D3 power state support per PC 2001 Design Guide.

Technical Context

The TSB43AB21AIPDT integrates a 1394a PHY transceiver and OHCI-compliant link-layer controller on a single die, with memory-mapped nonprefetchable registers aligned to OHCI Release 1.1. Its PHY layer uses an internal PLL locked to a 24.576-MHz crystal to generate 393.216-MHz reference and derive 49.152-MHz LLC synchronization clock.

It supports IEEE 1394a-2000 features including arbitration enhancements, power-down modes, and CIP header stripping for DV streams. The device implements TI-specific extensions at OHCI offset A88h for automatic DV/MPEG timestamp insertion and provides dedicated isochronous transmit/receive contexts with channel masking and fairness control.

Key Specifications

Pinout & Package

TSB43AB21AIPDT is housed in a 128-pin TQFP package (14 mm × 14 mm, 0.4 mm pitch) with exposed thermal pad. Pin assignments are defined per Figure 2–1 and Tables 2–1 through 2–8 of SLLS521A, covering PCI interface, PHY port (TPA/TPB), power, ground, and control signals.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 1394a OHCI host controller applications.

Compared with TSB43AB21AIPDT, TSB43AB22APDT offers scalable port count with zero software changes, while VT6306-LE trades DV acceleration for lower BOM cost in non-real-time data transfer use cases.

Availability

TSB43AB21AIPDT is available at Aetrix Electronics and suitable for digital video capture systems, portable media player hosts, industrial machine vision nodes, and battery-powered test equipment requiring stable component supply and long-term lifecycle support.

Supply support for TSB43AB21AIPDT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and connectivity solutions, with leadership in industrial, automotive, and communications markets.

The TSB43AB21AIPDT belongs to TI's 1394 Host Controller Solutions product line, designed specifically to enable robust, low-latency, power-efficient IEEE 1394a connectivity in PCI-based host systems.

FAQ

What is the primary function of the TSB43AB21AIPDT in a system?

The TSB43AB21AIPDT serves as a PCI-to-IEEE 1394a bridge, integrating both PHY transceiver and OHCI-compliant link-layer controller functions. It enables host systems to communicate with 1394 peripherals at S100/S200/S400 speeds while handling arbitration, isochronous scheduling, and power management per IEEE 1394a-2000 and OHCI Release 1.1. The TSB43AB21AIPDT manages all low-level 1394 protocol operations, freeing the host CPU from time-critical timing tasks.

Does the TSB43AB21AIPDT require an external crystal, and what frequency is needed?

Yes, the TSB43AB21AIPDT requires a 24.576-MHz fundamental-mode crystal connected to XI/XO pins; an external 24.576-MHz clock may substitute. This reference drives an internal PLL that generates the 393.216-MHz PHY clock and 49.152-MHz LLC clock. The TSB43AB21AIPDT does not operate with other crystal frequencies - deviation causes failure to lock PLL and loss of 1394 link functionality.

How does the TSB43AB21AIPDT support digital video applications?

The TSB43AB21AIPDT includes TI-specific hardware extensions at OHCI offset A88h to accelerate digital video workflows: it automatically inserts synchronization timestamps into transmitted DV/MPEG CIP packets and strips CIP headers from received DV streams. This offloads timestamp management from the CPU and ensures sub-microsecond timestamp accuracy - a capability confirmed in Section 5.2 and 5.3 of SLLS521A. The TSB43AB21AIPDT delivers deterministic timing essential for broadcast-grade video capture.

What power states does the TSB43AB21AIPDT support, and how is low-power mode triggered?

The TSB43AB21AIPDT supports PCI-defined D0 (fully active), D1, D2, and D3 (mechanical off) power states. Ultralow-power sleep mode activates automatically when the port is inactive (disconnected, disabled, or suspended) and the LPS bit (bit 19) in the Host Controller Control Register (OHCI offset 50h/54h) is cleared. In this mode, the PLL and most references shut down, yet TPBIAS detection remains active. The TSB43AB21AIPDT resumes full operation within 2 ms of setting LPS=1.

Can the TSB43AB21AIPDT be used in laptop designs with CardBus interfaces?

No - the TSB43AB21AIPDT is strictly a 33-MHz 32-bit PCI Local Bus device and lacks CardBus interface logic or voltage translation. While Section 9.8.1 of SLLS521A references CardBus PC Card clock specs, those apply only to timing validation methodology, not functional compatibility. The TSB43AB21AIPDT requires a native PCI slot or PCI-to-PCI bridge; integration into CardBus systems necessitates additional interface conversion hardware not supported by the TSB43AB21AIPDT itself.