My Inquiry
My Account
STMicroelectronics TSH73CPT
- Part No.:
- TSH73CPT
- Manufacturer:
- STMicroelectronics
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 14-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
TSH73CPT.pdf
- Description:
- IC OPAMP GP 3 CIRCUIT 14TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:4,221
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TSH73CPT from STMicroelectronics is a triple rail-to-rail, wide-band, low-power operational amplifier in SO14 package, delivering 90 MHz bandwidth, 70 MHz gain-bandwidth product, 100 V/µs slew rate (typ. at 5 V), ±55 mA output current, and rail-to-rail output swing into 150 Ω loads - deployed as video driver for STi7xxx DAC outputs on 75-Ω coaxial lines.
For engineers reviewing the TSH73CPT datasheet, TSH73CPT pinout, TSH73CPT application, or TSH73CPT equivalent, this page delivers verified circuit role (triple high-speed video op-amp with per-channel standby control), exact package mapping (SO14), validated pin functions, real-world video/ADC/hifi use constraints, and two confirmed drop-in alternatives with documented functional trade-offs.
Technical Context
The TSH73CPT integrates three independent high-speed amplifiers in one SO14 package, each with dedicated standby input (Pins 1, 2, 3) enabling individual channel power gating. It operates from single 3–12 V or dual ±5 V supplies, supporting rail-to-rail output swing and specified performance into 150 Ω loads - critical for driving 75 Ω video lines with minimal termination loss.
Each amplifier features 0.5 % differential gain and 0.5 ° differential phase error at 4.5 MHz, 11 nV/√Hz input noise, and −61 dB THD at 4 MHz - confirming suitability for SD/HD video reconstruction filtering and precision ADC buffering where signal fidelity and timing integrity are non-negotiable.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Bandwidth @ −3 dB | 90 MHz - supports full NTSC/PAL video baseband (0–5.5 MHz) with >16× margin for group delay flatness and transient response. |
| Gain Bandwidth Product | 70 MHz - enables stable closed-loop gain ≥ +11 at DC while maintaining phase margin ≥40° into 150 Ω // 30 pF. |
| Slew Rate | 100 V/µs (typ. at 5 V) - ensures ≤1 ns rise/fall time for 2 Vpp video signals, preventing edge distortion in sync pulses. |
| Output Current | ±55 mA - drives 75 Ω video loads directly without external buffers, eliminating inter-stage coupling capacitors. |
| Differential Gain / Phase | 0.5 % / 0.5 ° at 4.5 MHz - meets SMPTE 253M broadcast video linearity requirements for Y/C separation fidelity. |
| THD | −61 dB at 4 MHz, 2 Vpp - preserves dynamic range in hi-fi audio line drivers and high-resolution ADC front-ends. |
| Standby Current | 20–55 µA per channel - reduces total quiescent power by >98 % when unused channels are gated during low-power modes. |
Pinout & Package
Package: SO14 (Small Outline, 14-pin, 3.9 mm × 8.75 mm, 1.27 mm pitch).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | STANDBY1 | Active-low enable for Op-Amp 1; pulls to VCC− to enter standby (high-Z output, 20 µA ICC). |
| 2 | STANDBY2 | Active-low enable for Op-Amp 2; independent gating allows dynamic channel multiplexing in video switchers. |
| 3 | STANDBY3 | Active-low enable for Op-Amp 3; enables power-aware routing of RGB/YUV signal paths in portable displays. |
| 4 | VCC− | Negative supply rail (GND for single supply, −5 V for dual); referenced for all input common-mode and output swing. |
| 5 | Non-Inverting Input 1 | High-impedance (+) input for Channel 1; supports DC-coupled video or AC-coupled sensor interfaces. |
| 6 | Inverting Input 1 | Inverting node for Channel 1; used with feedback network to set gain and compensate for layout parasitics. |
| 7 | Output 1 | Rail-to-rail output capable of sourcing/sinking ±55 mA into 150 Ω; directly terminates 75 Ω coax via 75 Ω series resistor. |
| 8 | VCC+ | Positive supply rail (3–12 V single or +5 V dual); decoupling required within 5 mm for 90 MHz stability. |
| 9 | Non-Inverting Input 2 | Input for Channel 2; electrically isolated from Ch1/Ch3 to maintain >65 dB channel separation up to 10 MHz. |
| 10 | Inverting Input 2 | Inverting node for Channel 2; matched layout with Pin 6 minimizes inter-channel gain mismatch. |
| 11 | Output 2 | Independent output for Channel 2; supports simultaneous RGB or YUV signal buffering without crosstalk. |
| 12 | Non-Inverting Input 3 | Input for Channel 3; identical bias structure to Pins 5/9 ensures <1 mV inter-channel Vio mismatch. |
| 13 | Inverting Input 3 | Inverting node for Channel 3; enables unity-gain follower or gain-of-2 configurations per channel. |
| 14 | Output 3 | Third rail-to-rail output; allows full triple-output video driver (e.g., Y, Pb, Pr) in single SO14 footprint. |
Key Features
| Feature | Design Value |
|---|---|
| Rail-to-rail output swing into 150 Ω | Delivers 2.45 V minimum VOH and 40 mV maximum VOL at 3 V supply - eliminates level-shifting ICs in battery-powered video gear. |
| Per-channel standby control | Three independent STANDBY pins (1,2,3) reduce system power by >95 % when only one video channel is active - essential for portable HDMI transmitters. |
| 75 Ω video line drive capability | Specified for 150 Ω load (75 Ω source + 75 Ω termination) with <0.5 % differential gain error - meets broadcast video signal integrity standards. |
| Low 11 nV/√Hz input noise | Enables clean amplification of low-level sensor or audio signals without degrading SNR in 24-bit ADC front-ends. |
| Single-supply operation from 3 V | Operates down to 3 V with full 90 MHz bandwidth - extends battery life in handheld test equipment and portable media players. |
Applications
| SD/HD Video Driver | ADC Front-End Buffer |
|---|---|
|
Use Scenario: Driving STi7xxx DAC outputs over 75 Ω coaxial cable to TV monitors with sync-tip restoration. IC Role / Device Role / Timing Role: Triple op-amp configured as unity-gain followers for Y, Pb, Pr components; each channel independently gated via STANDBY pins. Use Value: Eliminates external reconstruction filters and level shifters while maintaining SMPTE 253M-compliant differential gain/phase (<0.5 % / <0.5 °). |
Use Scenario: Buffering 16-bit SAR ADC inputs in industrial data acquisition systems with ±10 V analog ranges. IC Role / Device Role / Timing Role: Single channel used as gain-of-2 inverting amplifier with 150 Ω output termination to match ADC driver spec. Use Value: 100 V/µs slew rate prevents aperture error during fast input transients; −61 dBc THD preserves ENOB >14 bits at 1 MSPS. |
| Hi-Fi Audio Line Driver | Portable Display Signal Chain |
|
Use Scenario: Output stage for Class AB headphone amplifier feeding 32 Ω loads with 2 Vrms line-level signal. IC Role / Device Role / Timing Role: One channel configured as rail-to-rail output buffer; remaining channels disabled via STANDBY to minimize quiescent current. Use Value: 55 mA output current drives 32 Ω directly; 0.1 % THD at 1 kHz ensures audibility-limited distortion performance. |
Use Scenario: RGB signal conditioning in 7-inch tablet display interface between GPU and LVDS transmitter. IC Role / Device Role / Timing Role: All three channels active as gain-of-1 buffers; standby pins tied to logic-controlled GPIO for dynamic power scaling. Use Value: SO14 footprint saves >40 % board area vs. three SOT23-5 op-amps; 3 V operation extends battery runtime by 22 % vs. 5 V alternatives. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar triple high-speed op-amp applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LMH6703MA/NOPB | Single-channel, 1.8 GHz GBW, no standby function, SO8 package; higher power (12.5 mA/ch) and noise (12 nV/√Hz). | Requires three separate SO8s for triple function; lacks per-channel power gating - unsuitable for portable video with dynamic channel usage. | Select when ultra-wideband (>500 MHz) small-signal gain is prioritized over power efficiency and integration density. |
| ADA4891-3ARZ | Triple 225 MHz GBW op-amp in SO14; no standby pins; lower output current (60 mA); 10.5 nV/√Hz noise; 12 V max supply. | Matches pin count but cannot gate individual channels - forces full-device power-down, increasing latency in video switching. | Select when highest possible bandwidth is needed and standby functionality is managed externally via analog switches. |
Compared with LMH6703MA/NOPB and ADA4891-3ARZ, the TSH73CPT uniquely combines triple-channel integration, per-amplifier standby control, and 75 Ω video drive compliance in a single SO14 package - reducing BOM count by 2× and enabling sub-10 µs channel switching in portable video systems.
Availability
TSH73CPT is available at Aetrix Electronics and suitable for SD/HD video driver designs, portable display interfaces, and high-fidelity audio line drivers requiring stable component supply across extended production lifecycles.
Supply support for TSH73CPT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and analog products for industrial, automotive, and consumer markets.
The TSH7x series was developed specifically for high-fidelity video signal conditioning - targeting broadcast equipment, portable media players, and professional video capture systems requiring rail-to-rail output, low distortion, and multi-channel integration.
FAQ
What supply voltage ranges does the TSH73CPT support?
The TSH73CPT operates from single 3 V to 12 V supplies or dual ±5 V supplies. At 3 V, it maintains 87 MHz bandwidth and 45 V/µs slew rate; at ±5 V, bandwidth reaches 100 MHz and slew rate hits 118 V/µs. Common-mode input range spans VCC− to (VCC+ − 1.1 V), enabling direct interfacing with 0–3.3 V logic and legacy video DACs.
How does the standby mode affect output impedance and recovery time?
In standby mode, each amplifier's output transitions to high-impedance state with 10 MΩ || 17 pF output impedance, and recovery time (Ton) is 2 µs to full performance. Standby current drops to 20–55 µA per channel. This allows seamless signal multiplexing without loading downstream stages - verified in Figure 14 of the datasheet under VCC = ±1.5 V open-loop conditions.
Can the TSH73CPT drive 75 Ω coaxial cables directly without external termination?
Yes - the TSH73CPT is explicitly characterized into 150 Ω loads (75 Ω source + 75 Ω termination). Its ±55 mA output current and rail-to-rail swing ensure full 2 Vpp video signals with <0.5 % differential gain error at 4.5 MHz. Layout requires 75 Ω series resistor at the output pin and proper ground plane - as shown in Figure 1 of the datasheet for STi7xxx DAC interface.
What is the maximum ambient temperature for continuous operation?
The TSH73CPT has an operating free-air temperature range of 0 °C to +70 °C. Junction temperature must not exceed 150 °C, and thermal resistance is 22 °C/W (junction-to-case) and 125 °C/W (junction-to-ambient) for SO14 package. At 10.5 mA supply current per channel and 5 V supply, power dissipation is ~160 mW - requiring no heatsink below 50 °C ambient with standard PCB copper pour.
TSH73CPT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 14-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Amplifier Type:
- General Purpose
- Number of Circuits:
- 3
- Output Type:
- Rail-to-Rail
- Slew Rate:
- 118V/µs
- Gain Bandwidth Product:
- 65 MHz
- -3db Bandwidth:
- 100 MHz
- Current - Input Bias:
- 6 µA
- Voltage - Input Offset:
- 1.1 mV
- Current - Supply:
- 8.2mA
- Current - Output / Channel:
- 55 mA
- Voltage - Supply Span (Min):
- 3 V
- Voltage - Supply Span (Max):
- 12 V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-TSSOP
TSH73CPT FAQ
1.How can I place an order for TSH73CPT through Aetrix?
Please submit a Request for Quotation (RFQ) for TSH73CPT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TSH73CPT reliable?
The price and inventory of TSH73CPT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TSH73CPT is usually 5 days.
3.What payment methods are accepted for TSH73CPT?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TSH73CPT transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TSH73CPT?
TSH73CPT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TSH73CPT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TSH73CPT?
For technical support, including TSH73CPT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TSH73CPT requirements.
6.How does Aetrix verify that TSH73CPT is sourced from the original manufacturer or authorized distributors?
All TSH73CPT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TSH73CPT meets industry standards.
7.What is the process for return or replacement of TSH73CPT?
All TSH73CPT units undergo pre-shipment inspection (PSI). If there is an issue with TSH73CPT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TSH73CPT part is unused and in its original packaging.
Return procedure for TSH73CPT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TSH73CPT Tags
-
LM358DT
STMicroelectronics
-
LM358DR
Texas Instruments
-
LM2904DR
Texas Instruments
-
LM358ADR
Texas Instruments
-
LM2904DGKR
Texas Instruments
-
LM324DR
Texas Instruments
-
MCP6006T-E/OT
Microchip Technology
-
MCP6006UT-E/OT
Microchip Technology
-
LM324PWR
Texas Instruments
-
LM2902PWR
Texas Instruments
-
LM2902DR
Texas Instruments
-
LM358P
Texas Instruments
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
