Renesas TSI350-66CQY

Overview

TSI350-66CQY from Integrated Device Technology is a PCI-to-PCI bridge IC designed to interconnect primary and secondary PCI buses in embedded computing and industrial backplane systems. It supports 33 MHz PCI bus operation on both sides, implements posted write and delayed transaction queuing, provides JTAG boundary-scan support, and enables hot-swap capability for CompactPCI applications.

For engineers reviewing the TSI350-66CQY datasheet, TSI350-66CQY pinout, TSI350-66CQY application, or TSI350-66CQY equivalent, this page delivers verified functional architecture, validated signal-level timing behavior, confirmed register-mapped configuration space, and real-world use cases in legacy PCI expansion and modular system design.

Technical Context

The TSI350-66CQY implements a dual-bus bridge with independent primary and secondary PCI interfaces, each compliant with PCI Local Bus Specification Rev 2.2. It features separate address/data phases, supports Type 0 and Type 1 configuration transactions, and performs automatic Type 1-to-Type 0 translation for downstream device enumeration.

Its internal architecture includes dedicated posted write, delayed transaction, and read data queues to decouple bus timing domains. The device integrates a JTAG TAP controller for IEEE 1149.1-compliant boundary-scan testing and supports synchronous or asynchronous secondary clocking modes for flexible timing integration.

Key Specifications

Pinout & Package

The TSI350-66CQY is housed in a 208-pin PQFP package with 0.5 mm pitch, optimized for high-density PCB layouts in industrial backplane and modular computing applications.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCI-to-PCI bridge applications.

Compared with PLX PCI9054 and Pericom PI7C9X20404AEX, the TSI350-66CQY uniquely delivers native dual-PCI-domain bridging with full Type 1 protocol handling, making it irreplaceable in legacy CompactPCI and industrial backplane designs where PCIe migration is not planned.

Availability

TSI350-66CQY is available at Aetrix Electronics and suitable for industrial backplane expansion, modular test equipment, and legacy system migration requiring stable component supply and long-term obsolescence management.

Supply support for TSI350-66CQY includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Integrated Device Technology (IDT), now part of Renesas Electronics, is a fabless semiconductor company specializing in timing, interface, and memory solutions for communications, computing, and industrial markets.

The TSI350-66CQY belongs to IDT's PCI interconnect product line, engineered specifically for robust, standards-compliant bridging in mission-critical embedded systems where reliability, hot-swap capability, and long-lifecycle support are mandatory.

FAQ

What is the maximum supported clock frequency for the TSI350-66CQY primary and secondary PCI interfaces?

The TSI350-66CQY supports 33 MHz operation on both primary and secondary PCI buses, fully compliant with PCI Local Bus Specification Revision 2.2. It does not support 66 MHz operation - the "66" in the part number refers to the commercial temperature grade (0°C to +70°C), not bus speed. All timing parameters, including setup/hold and propagation delays, are validated at 33 MHz.

Does the TSI350-66CQY support PCI Express or only legacy PCI?

The TSI350-66CQY supports PCI Local Bus Specification Revision 2.2 only - it is a native PCI-to-PCI bridge with no PCIe physical layer or protocol logic. It cannot interface directly with PCIe endpoints or root complexes. For PCIe-to-PCI bridging, a different device such as the Pericom PI7C9X20404AEX would be required.

How does the TSI350-66CQY handle configuration space access for downstream devices?

The TSI350-66CQY implements full Type 1 configuration transaction handling: it forwards Type 1 requests to secondary bus devices, translates them to Type 0 for local configuration space access, and routes responses back through the bridge. This enables standard PCI enumeration software to discover and configure all downstream devices without modification.

Can the TSI350-66CQY operate with asynchronous clocks on primary and secondary buses?

Yes - the TSI350-66CQY supports both synchronous and asynchronous secondary clock modes. In asynchronous mode, the secondary clock (CLKOUT) may run independently of CLKIN, enabling operation across clock domains with no phase alignment requirement. This is essential for hot-swap and mixed-timing backplane designs.

Is JTAG boundary-scan supported on the TSI350-66CQY, and what level of IEEE 1149.1 compliance does it provide?

Yes - the TSI350-66CQY integrates a full IEEE 1149.1-compliant JTAG TAP controller with boundary-scan register, instruction register, and bypass register. It supports EXTEST, SAMPLE/PRELOAD, and BYPASS instructions, enabling board-level interconnect testing and in-system debugging without functional initialization.