Renesas TSI350A-66CLV

Overview

TSI350A-66CLV from Integrated Device Technology is a 32-bit, 66 MHz PCI-to-PCI bridge IC compliant with PCI Local Bus Specification Revision 2.3. It features dual asynchronous PCI interfaces, supports up to nine bus masters on its secondary interface, provides ten independent secondary clock outputs, and enables concurrent primary/secondary bus operation for traffic isolation in multimedia systems.

For engineers reviewing the TSI350A-66CLV datasheet, TSI350A-66CLV pinout, TSI350A-66CLV application, or TSI350A-66CLV equivalent, key selection considerations include secondary bus arbitration support, Hot Swap capability per CompactPCI, D3Hot power management, VGA/Palette memory decoding options, and compatibility with Intel/TI/PLX/Pericom legacy bridges.

Technical Context

The TSI350A-66CLV implements two fully independent PCI interfaces - primary and secondary - each capable of acting as bus master or slave depending on transaction type. Its internal architecture includes separate posted/non-posted buffers and queues, address decoder, secondary bus arbiter, and mux logic to manage bidirectional data/control flow between buses.

It supports asynchronous clocking between interfaces, external clock sourcing or primary-clock derivation for secondary clocks, GPIO-controlled clock masking at power-up, and four independent delayed transactions per direction. The device also implements PCI bus locking and optional non-posted entry flush on same-direction posted writes.

Key Specifications

Pinout & Package

TSI350A-66CLV is packaged in a 208-pin Plastic Quad Flat Package (PQFP) with 0.5 mm pitch and 28 × 28 mm body size. Pin functions are defined per IDT document 80D5000_FB001_07 and include dedicated REQ#/GNT# pairs for secondary arbitration, CLKOUTx outputs, JTAG boundary-scan pins (TCK/TMS/TDI/TDO), and GPIO-controlled clock mask inputs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCI-to-PCI bridge applications.

Compared with PLX PCI9054-AC50BI and Pericom PI7C9X110BQF, the TSI350A-66CLV delivers superior secondary bus scalability (9 masters, 10 clocks), tighter integration of CompactPCI Hot Swap, and native support for external secondary arbitration - making it optimal for high-density industrial backplanes and multi-function video cards.

Availability

TSI350A-66CLV is available at Aetrix Electronics and suitable for industrial PC backplanes, video capture cards, and embedded video recorders requiring stable component supply and long-term lifecycle support.

Supply support for TSI350A-66CLV includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Integrated Device Technology (IDT) is a fabless semiconductor company specializing in timing, interface, and memory connectivity solutions for communications, computing, and industrial markets.

The TSI350A-66CLV belongs to IDT's PCI interconnect product line, designed specifically to extend PCI system capacity while maintaining full specification compliance and enabling robust Hot Swap-capable expansion in mission-critical embedded platforms.

FAQ

What PCI specification revision does the TSI350A-66CLV implement?

The TSI350A-66CLV implements PCI Local Bus Specification Revision 2.3. This ensures full compatibility with standard PCI host bridges, peripherals, and system software stacks developed for that revision. It supports all mandatory transaction types, configuration space access, and electrical signaling requirements defined in Rev 2.3 - including 66 MHz timing and 32-bit addressing. No firmware or driver modifications are required for Rev 2.3-compliant systems using the TSI350A-66CLV.

Does the TSI350A-66CLV support asynchronous clocking between primary and secondary PCI buses?

Yes, the TSI350A-66CLV supports fully asynchronous operation between its primary and secondary PCI interfaces. The secondary clock can be derived from the primary clock input or supplied independently via an external source. This enables flexible system timing architectures - for example, running the primary bus at 66 MHz while driving secondary slots at 33 MHz for legacy device compatibility. Clock domain crossing is handled internally with handshake synchronization.

How many PCI bus masters can the TSI350A-66CLV support on its secondary interface?

The TSI350A-66CLV supports up to nine PCI bus masters on its secondary interface, with dedicated REQ#/GNT# signal pairs (REQ0#–REQ8# and GNT0#–GNT8#). This allows a single TSI350A-66CLV-based option card to host multiple PCI devices - such as video encoders, network controllers, and storage adapters - without violating PCI loading rules. External arbitration logic may be used to scale beyond nine if needed.

What Hot Swap capability does the TSI350A-66CLV provide?

The TSI350A-66CLV implements CompactPCI Hot Swap functionality per PICMG 2.1, including support for insertion/removal detection, power fault monitoring, and controlled power sequencing on the secondary bus. It integrates JTAG boundary-scan (IEEE 1149.1) for interconnect testing and uses GPIO-controlled clock masking to safely gate secondary clocks during hot insertion. This makes the TSI350A-66CLV suitable for carrier-grade telecom and industrial systems requiring zero-downtime maintenance.

Is the TSI350A-66CLV compatible with legacy PCI bridge solutions from other vendors?

Yes, the TSI350A-66CLV is explicitly documented as compatible with existing solutions from Intel, TI, PLX, and Pericom. Its register map, configuration space layout, and transaction behavior align with industry-standard PCI-to-PCI bridge implementations, enabling drop-in replacement in many designs. However, pinout and clocking configurations differ - so PCB layout and BIOS/firmware initialization sequences must be verified against the TSI350A-66CLV datasheet before substitution.