STMicroelectronics TSM1014AIST

Overview

TSM1014AIST from STMicroelectronics is a dual operational amplifier-based CV/CC controller IC for secondary-side feedback in flyback SMPS, integrating a 1.25 V ±0.5% voltage reference, two transconductance op-amps (Gm = 0.5–1 mA/mV), 4.5–28 V operation, and 100–180 µA supply current. It enables precise voltage regulation (e.g., 4.1 V output) and current limiting (e.g., battery charge termination) in compact AC/DC adapters and USB-C chargers.

For engineers reviewing the TSM1014AIST datasheet, TSM1014AIST pinout, TSM1014AIST application, or TSM1014AIST equivalent, key selection criteria include its dual-opamp architecture with independent CV/CC loop control, sink-only outputs enabling ORing behavior, 2 kV HBM ESD rating, and MiniSO-8 thermal resistance (180 °C/W) for thermally constrained designs.

Technical Context

The TSM1014AIST implements two independent transconductance operational amplifiers: one configured as a voltage controller (CV) using Vref and pins CV−/CVOUT, and another as a current limiter (CC) using CC−/CC+/CCOUT with external Rsense and resistor divider biasing. Both op-amps feature rail-to-rail input common-mode range (0 to Vcc−1.5 V) and are optimized for optocoupler-driven feedback loops.

Its internal 1.25 V reference (±0.5% at 25°C, ±30 mV over −40 to +105°C) supplies both op-amp bias networks. The sink-only output stage (Ios = 5–10 mA, Vol = 250–400 mV @ 5 mA) eliminates need for external pull-ups and supports direct optocoupler LED drive. Supply rejection (65–100 dB) and low offset drift (7 µV/°C) ensure stability across line and temperature variations.

Key Specifications

Pinout & Package

Package: MiniSO-8 (plastic micropackage), 3.8 mm × 4.9 mm body, 1.27 mm pitch, 180 °C/W R_thJA.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar CV/CC controller applications.

Compared with TL431+LM358 and UCC28063, the TSM1014AIST uniquely delivers matched dual op-amps with a common precision reference in a single MiniSO-8 package-enabling compact, thermally stable, optocoupler-based CV/CC control unattainable with discrete or primary-side alternatives.

Availability

TSM1014AIST is available at Aetrix Electronics and suitable for USB PD adapters, smartphone fast chargers, and industrial DC power supplies requiring stable component supply, long-term lifecycle support, and RoHS-compliant MiniSO-8 packaging.

Supply support for TSM1014AIST includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and analog products for automotive, industrial, and consumer markets.

The TSM1014 belongs to ST's dedicated SMPS secondary-side controller product line, engineered specifically for cost-sensitive, space-constrained flyback converters needing accurate dual-loop regulation without complex digital control.

FAQ

What is the maximum allowable voltage on the Vcc pin?

The absolute maximum rating for Vcc is 28 V, enforced by an internal Zener clamp. Operation above this voltage risks permanent damage. In practice, Vcc should be limited to ≤27 V under worst-case transient conditions, especially when derived from an auxiliary winding without external clamping.

Can TSM1014AIST drive an optocoupler directly without a series resistor?

No. The sink-output stage requires an external current-limiting resistor between CVOUT/CCOUT and the optocoupler LED anode. For typical PC817-type optocouplers (IF = 5 mA), a 1 kΩ resistor is recommended at Vcc = 12 V to ensure reliable turn-on while staying within the 5–10 mA short-circuit current limit.

How does the 0.5% reference tolerance affect current limit accuracy?

Current limit accuracy depends directly on VRef tolerance because the CC+ input voltage is derived from a resistor divider tied to VRef. With 0.5% VRef tolerance and matched 1% resistors, total current limit error is typically ≤3% over temperature-sufficient for Class II adapter certifications requiring ±5% I_lim.

Is there a recommended PCB layout guideline for minimizing noise coupling into CV− and CC−?

Yes: route CV− and CC− traces away from switching nodes and power planes; use guard rings tied to Gnd around these pins; place the VRef bypass capacitor (100 nF X7R) within 2 mm of Pin 1; and avoid sharing Gnd return paths between Rsense and output voltage dividers to prevent common-impedance coupling.