STMicroelectronics TSM101IDT

Overview

TSM101IDT from STMicroelectronics is a dual-loop voltage and current controller IC for secondary-side feedback in isolated SMPS, integrating a 1.24V ±1% precision bandgap reference, two ORed op-amps (1MHz GBW), and an enableable 1.4mA current source. It operates from 4.5V to 32V supply, delivers up to 10mA reference output, and targets battery chargers requiring simultaneous CV/CC regulation with optocoupler-driven PWM control.

For engineers reviewing the TSM101IDT datasheet, TSM101IDT pinout, TSM101IDT application, or TSM101IDT equivalent, this device serves as a drop-in functional upgrade over TL431-based designs where precise dual-loop regulation, temperature-stable current limiting, and integrated offset capability are required - especially in NiCd/NiMH charger topologies with programmable charge profiles.

Technical Context

The TSM101IDT implements two independent regulation loops sharing a single 1.24V reference: one compares scaled output voltage (via R6/R7 divider) to Vref at Pin 1, the other compares sense-resistor voltage (at Pin 5) to Vref-derived threshold set by R2/R3. Both op-amp outputs are internally ORed at Pin 6, enabling priority-based control where current-limiting action overrides voltage regulation during overload.

Its built-in current generator (Pin 2 enable input) injects 1.4mA into the current-sense node when Pin 2 voltage drops below 0.6V, allowing programmable current offset without external components. The SO8 package supports surface-mount assembly while maintaining DIP8-compatible pinout and thermal performance up to 105°C ambient.

Key Specifications

Pinout & Package

SO8 (Plastic Micropackage), 150°C max junction temperature, θ_JA = 130–200°C/W.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar voltage and current controller applications.

Compared with TL431+LM358, TSM101IDT reduces layout complexity and improves loop coordination; versus UC3907, it provides complete dual-loop integration at lower cost but with relaxed reference accuracy (1% vs 0.5%).

Availability

TSM101IDT is available at Aetrix Electronics and suitable for battery chargers, isolated AC/DC adapters, voltage supervisors, and industrial SMPS requiring stable component supply with guaranteed long-term sourcing.

Supply support for TSM101IDT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, microcontroller, power, and sensor solutions for industrial, automotive, and consumer markets.

The TSM101 product line was developed specifically for cost-sensitive, high-reliability secondary-side feedback in offline SMPS - targeting battery charging, adapter, and industrial power applications where integration, precision, and thermal robustness are critical.

FAQ

What is the maximum allowable load on the Vref pin?

The Vref pin (Pin 1) is rated for up to 10mA output current per datasheet specifications. Exceeding this draws excessive current from the internal bandgap circuit, causing reference voltage droop and thermal drift. For resistor-divider biasing, ensure total divider current remains ≤8mA - e.g., use ≥150Ω minimum total resistance when Vref = 1.24V.

How does the ORed output behavior affect loop stability?

The internal OR logic forces the OUTPUT pin (Pin 6) low whenever either op-amp output goes low, giving current limiting priority. This eliminates race conditions between loops and simplifies compensation - only one dominant pole (from the active loop) governs response, avoiding dual-loop interaction that causes ringing or overshoot in discrete implementations.

Can Pin 2 (Csen) be driven by a microcontroller GPIO?

Yes - Pin 2 accepts TTL-compatible logic levels. Driving it low (≤0.6V) enables the 1.4mA current source; pulling it high (>2V) disables it. A 10kΩ pull-up to Vcc suffices for default-disable operation. No level-shifting is needed for 3.3V or 5V MCU I/O, as input leakage is <30µA and thresholds are voltage-defined, not rail-ratio dependent.

What is the recommended bypass capacitor for Vcc (Pin 8)?

A 10µF aluminum or tantalum capacitor (C4) is specified for Vcc bypassing, placed within 5mm of Pin 8. This value suppresses low-frequency ripple from auxiliary windings while complementing the 100nF high-frequency capacitor (C3) used for loop compensation. Using only ceramic capacitance risks insufficient bulk energy storage during line transients, leading to Vcc brownout and regulation dropout.