STMicroelectronics TSV772IYDT
- Part No.:
- TSV772IYDT
- Manufacturer:
- STMicroelectronics
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
TSV772IYDT.pdf
- Description:
- HIGH BANDWIDTH (20MHZ) LOW OFFSE
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
TSV772IYDT from STMicroelectronics is a dual, rail-to-rail input/output operational amplifier optimized for high-bandwidth precision signal conditioning in automotive and industrial systems. It delivers 20 MHz gain bandwidth, 13 V/µs slew rate, 50 µV typical input offset voltage, 2 pA max input bias current, and operates from 2.0 V to 5.5 V supply - enabling accurate low-side/high-side current sensing and photodiode amplification in battery-powered solar management systems.
For engineers reviewing the TSV772IYDT datasheet, TSV772IYDT pinout, TSV772IYDT application, or TSV772IYDT equivalent, key selection criteria include its guaranteed 200 µV max input offset over –40 °C to +125 °C, 4 kV HBM ESD rating, 7 nV/√Hz noise at 10 kHz, unity-gain stability with 47 pF capacitive load, and dual-channel MiniSO8 packaging for space-constrained PCB layouts.
Technical Context
The TSV772IYDT integrates two independent, fully matched amplifier channels with complementary differential input pairs enabling rail-to-rail common-mode operation from VCC– – 0.2 V to VCC+ + 0.1 V. Its architecture prioritizes low-input-bias-current FET inputs and precision trimming to achieve <200 µV offset across temperature, making it suitable for DC-coupled sensor interfaces where drift-induced error must be minimized.
Each channel features 20 MHz unity-gain bandwidth with 50° phase margin and 9 dB gain margin, ensuring stable operation in unity-gain buffers and active filters. The device supports full-swing output drive into 10 kΩ loads while maintaining 10 mV output saturation voltage at 25 °C - critical for A/D converter input buffering in 3.3 V and 5 V data acquisition systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Gain Bandwidth Product | 20 MHz - enables stable closed-loop operation up to 100 kHz with gain ≥200, supporting high-speed current sensing and anti-aliasing filtering. |
| Input Offset Voltage | 200 µV max (–40 °C to +125 °C) - ensures sub-0.1% measurement error in 100 mV full-scale current shunt applications without calibration. |
| Slew Rate | 13 V/µs - supports 1 V step response settling within 300 ns to 0.1%, critical for fast transient detection in motor control feedback loops. |
| Supply Voltage Range | 2.0 V to 5.5 V - allows direct interface with Li-ion, 3.3 V MCU I/O, and legacy 5 V systems without level-shifting circuitry. |
| Input Bias Current | 2 pA max at 25 °C - preserves signal integrity in high-impedance photodiode and piezoelectric sensor front-ends. |
| Output Drive | ±65 mA per channel at 25 °C - drives 10 kΩ ADC input buffers and 47 pF capacitive loads without external isolation resistors. |
| ESD Rating | 4 kV HBM - meets automotive electronics robustness requirements for in-vehicle signal conditioning modules. |
| Operating Temperature | –40 °C to +125 °C - qualified for under-hood automotive and industrial power conversion environments. |
Pinout & Package
TSV772IYDT is packaged in MiniSO8 (8-pin SOIC narrow, 3.9 mm width), a surface-mount package with standard footprint compatibility and thermal resistance of 127 °C/W (junction-to-ambient).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | OUT1 | Amplified output of Channel 1; rail-to-rail swing supports direct connection to SAR ADC reference buffers. |
| 2 | IN1– | Inverting input of Channel 1; matched to IN1+ for <200 µV offset, used in transimpedance and difference amplifier configurations. |
| 3 | IN1+ | Non-inverting input of Channel 1; FET-based input enables <2 pA bias current for photodiode biasing. |
| 4 | VCC– | Negative supply rail; connects to system ground or negative rail; exposed pad (if DFN variant) may tie here. |
| 5 | IN2+ | Non-inverting input of Channel 2; electrically identical to IN1+, enabling dual-sensor synchronous sampling. |
| 6 | IN2– | Inverting input of Channel 2; supports independent gain configuration per channel without crosstalk. |
| 7 | OUT2 | Amplified output of Channel 2; isolated from OUT1 to prevent inter-channel loading in multi-channel DAQ designs. |
| 8 | VCC+ | Positive supply rail; accepts 2.0–5.5 V; internal regulation ensures consistent GBP and SR across voltage range. |
Key Features
| Feature | Design Value |
|---|---|
| Rail-to-rail input and output | Operates with Vicm from VCC– – 0.2 V to VCC+ + 0.1 V and VOUT swing within 10 mV of rails - maximizes dynamic range in single-supply 3.3 V systems. |
| Low input offset drift | ±5 µV/°C max - limits total offset error to <1.25 mV over full –40 °C to +125 °C range, eliminating need for periodic recalibration. |
| High EMI rejection | EMIRR > 70 dB from 400 MHz to 2.4 GHz - suppresses RF rectification artifacts in noisy automotive CAN/LIN bus environments. |
| Unity-gain stable with 47 pF load | Characterized for CL = 47 pF at AV = 1 - simplifies ADC driver design without requiring external compensation networks. |
| Automotive grade qualification | AEC-Q100 Grade 1 (–40 °C to +125 °C) - certified for engine control, battery monitoring, and ADAS sensor signal chains. |
| Low noise density | 7 nV/√Hz at 10 kHz - enables resolution of µV-level signals in precision current sensing with 100 Ω shunts. |
Applications
| High-Bandwidth Current Sensing | Photodiode Signal Amplification |
|---|---|
|
Use Scenario: Real-time phase current monitoring in 48 V BLDC motor inverters using low-value (1–5 mΩ) shunt resistors. IC Role / Device Role / Timing Role: Dual-channel TSV772IYDT configures one op amp as a high-side current sense amplifier and the other as a low-side reference buffer, synchronizing measurements within 100 ns. Use Value: 20 MHz bandwidth captures PWM edge transients; 200 µV offset ensures <0.5% full-scale error at 10 A nominal current without trimming. |
Use Scenario: Converting weak photocurrent (100 pA–10 nA) from UV-enhanced Si photodiodes in portable gas analyzers. IC Role / Device Role / Timing Role: Configured as transimpedance amplifier (TIA) with 10 MΩ feedback resistor; second channel buffers filtered output for 16-bit SAR ADC. Use Value: 2 pA input bias current prevents dark-current error; 7 nV/√Hz noise maintains SNR > 85 dB at 1 kHz modulation frequency. |
| A/D Converter Input Buffer | Automotive Signal Conditioning |
|
Use Scenario: Driving the input of a 1 MSPS, 12-bit successive-approximation ADC in a solar microinverter's DC-link voltage monitor. IC Role / Device Role / Timing Role: Unity-gain buffer isolating high-impedance voltage divider from ADC sample capacitor; second channel conditions auxiliary temperature sensor signal. Use Value: 13 V/µs slew rate settles 1 V step in <300 ns to 0.1%; 47 pF load tolerance eliminates need for series RISO, preserving DC accuracy. |
Use Scenario: Amplifying differential signals from Hall-effect position sensors in EPS (electric power steering) control modules. IC Role / Device Role / Timing Role: Dual-channel configuration processes left/right sensor pairs simultaneously, rejecting common-mode EMI from nearby 3-phase inverter switching. Use Value: 4 kV HBM ESD rating withstands assembly handling; 125 °C operation sustains reliability near steering column heat sources. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual high-bandwidth precision op amp applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TSV792IDT | 50 MHz GBW, 22 V/µs SR, 300 µV max Vio, same MiniSO8 package | Better for wideband active filters and RF envelope detection; higher offset reduces DC accuracy in shunt sensing | Select when bandwidth >30 MHz required and offset <100 µV is not mandatory |
| LMV722MMX/NOPB | 10 MHz GBW, 5.5 V/µs SR, 500 µV max Vio, 2.7–5.5 V supply, same pinout | Limited by lower speed and higher offset; suitable only for <100 kHz sensor buffering | Choose only for cost-sensitive non-automotive designs where 20 MHz performance is unnecessary |
Compared with TSV772IYDT, TSV792IDT trades offset precision for bandwidth headroom, while LMV722MMX sacrifices both speed and accuracy for legacy compatibility - making TSV772IYDT the optimal balance for automotive-grade 20 MHz sensing with <200 µV error budget.
Availability
TSV772IYDT is available at Aetrix Electronics and suitable for high-bandwidth current sensing, photodiode amplification, and A/D converter buffering requiring stable component supply across automotive, solar energy, and industrial embedded programs.
Supply support for TSV772IYDT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, microcontroller, power, and sensor solutions for automotive, industrial, and consumer markets.
The TSV77x family targets high-accuracy, high-speed signal conditioning in harsh-environment applications - specifically engineered for automotive current sensing, photodiode interfaces, and precision ADC drivers operating from 2.0 V to 5.5 V.
FAQ
What is the maximum capacitive load the TSV772IYDT can drive without external compensation?
The TSV772IYDT is fully characterized and stable driving up to 47 pF in unity-gain configuration, as verified in DS13842 Rev 7. For loads exceeding 47 pF, a 10–33 Ω series isolation resistor (RISO) at the output is recommended to suppress peaking and ringing while preserving DC accuracy - no internal compensation network is required.
Does the TSV772IYDT support true rail-to-rail input common-mode range?
Yes - the TSV772IYDT accepts input voltages from VCC– – 0.2 V to VCC+ + 0.1 V, covering the full supply range and extending 200 mV beyond both rails. Its dual-input-pair architecture enables seamless transition across the entire range, though optimal CMRR (>90 dB) is maintained between VCC– – 0.1 V and VCC+ – 1.8 V.
Can unused channels be left floating?
No - unused channels must be configured to avoid oscillation and excess current draw. STMicroelectronics specifies two valid configurations: (1) unity-gain buffer with inputs tied within Vicm range, or (2) open-loop comparator with ≥100 mV differential input. Leaving inputs unconnected violates absolute maximum ratings and risks instability on active channels.
Is the TSV772IYDT qualified for automotive applications?
Yes - the TSV772IYDT is AEC-Q100 Grade 1 qualified (–40 °C to +125 °C), with full characterization across temperature, 4 kV HBM ESD rating, and automotive-specific reliability testing including HTOL and temperature cycling. It is explicitly listed in ST's automotive-grade portfolio for EPS, battery monitoring, and ADAS subsystems.
TSV772IYDT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Amplifier Type:
- General Purpose
- Number of Circuits:
- 2
- Output Type:
- Rail-to-Rail
- Slew Rate:
- 13V/µs
- Gain Bandwidth Product:
- 20 MHz
- -3db Bandwidth:
- -
- Current - Input Bias:
- 2 pA
- Voltage - Input Offset:
- 200 µV
- Current - Supply:
- 1.9mA (x2 Channels)
- Current - Output / Channel:
- 65 mA
- Voltage - Supply Span (Min):
- 2 V
- Voltage - Supply Span (Max):
- 5.5 V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SO
TSV772IYDT FAQ
1.How can I place an order for TSV772IYDT through Aetrix?
Please submit a Request for Quotation (RFQ) for TSV772IYDT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TSV772IYDT reliable?
The price and inventory of TSV772IYDT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TSV772IYDT is usually 5 days.
3.What payment methods are accepted for TSV772IYDT?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TSV772IYDT transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TSV772IYDT?
TSV772IYDT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TSV772IYDT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TSV772IYDT?
For technical support, including TSV772IYDT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TSV772IYDT requirements.
6.How does Aetrix verify that TSV772IYDT is sourced from the original manufacturer or authorized distributors?
All TSV772IYDT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TSV772IYDT meets industry standards.
7.What is the process for return or replacement of TSV772IYDT?
All TSV772IYDT units undergo pre-shipment inspection (PSI). If there is an issue with TSV772IYDT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TSV772IYDT part is unused and in its original packaging.
Return procedure for TSV772IYDT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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