Texas Instruments TUSB9261IPVP
- Part No.:
- TUSB9261IPVP
- Manufacturer:
- Texas Instruments
- Category:
- Specialized
- Package:
- 64-TQFP Exposed Pad
- Datasheet:
-
TUSB9261IPVP.pdf
- Description:
- IC INTFACE SPECIALIZED 64HTQFP
- Quantity:
- Payment:

- Shipping:

Inventory:233
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Product details
Overview
TUSB9261IPVP from Texas Instruments is a USB 3.0 to SATA II bridge IC integrating an ARM Cortex-M3 microcontroller, SuperSpeed USB 3.0 PHY, SATA Gen II (3.0 Gbps) PHY, AHCI controller, and 64 kB ROM + 80 kB RAM. It supports UASP and BOT mass storage protocols and enables external HDD/SSD connectivity via USB 3.0 host ports with full SATA link negotiation (Gen1i/m, Gen2i/m).
For engineers reviewing the TUSB9261IPVP datasheet, TUSB9261IPVP pinout, TUSB9261IPVP application, or TUSB9261IPVP equivalent, key selection considerations include its dual-power rail operation (1.1 V / 3.3 V), 40 MHz crystal/oscillator clock support, JTAG debug interface, and configurable GPIO/PWM for LED status indication in portable storage designs.
Technical Context
The TUSB9261IPVP implements a tightly coupled bridge architecture where the embedded ARM Cortex-M3 executes firmware-loaded-from-SPI-flash to manage USB device enumeration (UASP/BOT/HID), SATA link training (OOB sequence, speed negotiation), and AHCI register configuration. Its USB 3.0 PHY includes adaptive equalization for jitter tolerance, while the SATA PHY complies fully with SATA Revision 2.6.
Power management is handled through USB-defined U-states (U0–U3) and SATA partial/slumber states, coordinated by firmware. Clock generation uses a single 40 MHz reference (crystal or oscillator) feeding internal PLLs for USB 3.0 (125 MHz), USB 2.0 (48 MHz), and SATA (75/150 MHz), eliminating need for multiple clock sources.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| USB Interface | SuperSpeed (5 Gbps), HS (480 Mbps), FS (12 Mbps); supports UASP, BOT, HID classes |
| SATA Interface | SATA II Gen1/Gen2 (1.5/3.0 Gbps); AHCI-compliant; supports ATA/ATAPI-8 devices |
| Core Processor | ARM Cortex-M3 @ up to 40 MHz; 64 kB ROM boot code + 80 kB RAM for firmware execution |
| Power Supply | 1.1 V (VDD) + 3.3 V (VDD33/VDDA33); typical active current: 291 mA @ VDD11 + 65 mA @ VDD33 (SS mode) |
| Clock Source | 40 MHz crystal or oscillator; integrated spread-spectrum clock generation; ±50 ppm frequency tolerance |
| ESD Rating | HBM ±2000 V, CDM ±1500 V - meets industrial handling requirements without external protection |
| Operating Temp | –40°C to +85°C (industrial grade); junction temperature limit: 100°C |
Pinout & Package
Package: HTQFP-64 (7.0 mm × 7.0 mm, 0.5 mm pitch), RoHS-compliant, with exposed thermal pad (Pin 65 = VSS).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| GRSTz (Pin 4) | Global reset input | Active-low synchronous reset; must be held low ≥2 ms after power rails stabilize |
| USB_SSTXP/USB_SSTXM (Pins 43/42) | SuperSpeed USB TX differential pair | 5-Gbps transmit path; requires controlled 90-Ω differential impedance routing |
| USB_SSRXP/USB_SSRXM (Pins 46/45) | SuperSpeed USB RX differential pair | Adaptive equalizer enables robust reception under >1000 ps peak-to-peak jitter |
| SATA_TXP/SATA_TXM (Pins 57/56) | SATA Gen II TX differential pair | 3-Gbps transmitter; polarity swap supported in TI reference design for PCB routing simplification |
| SATA_RXP/SATA_RXM (Pins 60/59) | SATA Gen II RX differential pair | Supports SATA OOB detection and link speed negotiation (1.5/3.0 Gbps) |
| SPI_CS0/SPI_SCLK/SPI_DATA_IN/OUT (Pins 21/17/20/18) | SPI master interface | Loads firmware from external SPI flash at power-up; CS0 dedicated to flash, CS1/CS2 configurable as GPIO |
| GPIO[11:0] / PWM0/PWM1 (Pins 23,22,6,5,16,15,14,13,11,10,9,8,2,3) | Configurable I/O | 12 GPIOs; two support PWM for LED blink/dimming; default firmware maps GPIO1/GPIO5 to USB link state |
| JTAG_TCK/TDI/TDO/TMS/TRSTz (Pins 25–29) | IEEE 1149.1/1149.6 boundary scan | Enables silicon-level debug, firmware validation, and production test without custom tooling |
Key Features
| Feature | Design Value |
|---|---|
| Integrated USB 3.0 + SATA II Bridge | Eliminates need for separate USB device controller and SATA host controller ICs; reduces BOM count and PCB area |
| UASP + BOT Dual-Mode Firmware | Enables high-throughput UASP (with NCQ) when host supports it; falls back to legacy BOT for broad OS compatibility |
| ARM Cortex-M3 with 80 kB RAM | Allows field-upgradable firmware via USB; supports custom HID functions (e.g., one-touch backup button) |
| Single 40 MHz Clock Source | Reduces system cost and layout complexity; integrated SSCG meets USB 3.0 spectral mask requirements |
| Configurable GPIO/PWM Outputs | 12 GPIOs and 2 PWM channels enable direct LED control for USB link status, disk activity, and power fault indication |
| JTAG + UART Debug Interfaces | Full visibility into firmware execution and protocol stack behavior during development and failure analysis |
Applications
| External HDD Enclosure | Portable SSD Dock |
|---|---|
Use Scenario: 2.5-inch SATA HDD housed in aluminum enclosure with USB 3.0 Type-A upstream port. IC Role / Device Role / Timing Role: TUSB9261IPVP acts as USB device controller and SATA host adapter, managing BOT/UASP command translation and link-layer timing alignment between USB and SATA domains. Use Value: Enables plug-and-play Windows/macOS/Linux compatibility with sustained 300+ MB/s throughput using UASP and native command queuing on HDDs. |
Use Scenario: Bus-powered M.2 SATA SSD dock supporting hot-swap and TRIM passthrough. IC Role / Device Role / Timing Role: TUSB9261IPVP serves as protocol bridge and power manager, negotiating UASP interface and enforcing SATA slumber state during USB suspend (U3). Use Value: Delivers 450+ MB/s sequential reads with <50 µs command latency and extends SSD lifespan via TRIM and LPM support. |
| Optical Drive Adapter | Industrial Data Logger |
Use Scenario: USB-connected SATA DVD±RW drive for kiosk or media playback systems. IC Role / Device Role / Timing Role: TUSB9261IPVP handles ATAPI command translation, USB mass storage class enumeration, and optical drive motor power sequencing via GPIO-controlled enable lines. Use Value: Supports all 13 BOT error cases per specification, ensuring robust error recovery during disc insertion/ejection and buffer underrun conditions. |
Use Scenario: Ruggedized field recorder using SATA SSD for continuous video capture over USB 3.0. IC Role / Device Role / Timing Role: TUSB9261IPVP operates as deterministic real-time bridge, using watchdog timer and UART debug to maintain data integrity during voltage dips or ESD events. Use Value: Industrial temp range (–40°C to +85°C), 100% tested ESD rating, and JTAG traceability ensure reliable operation in uncontrolled environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar USB-to-SATA bridge applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ASMedia ASM1083 | PCIe-to-PCI bridge only; no USB or SATA functionality - requires companion USB 3.0 host controller and SATA controller ICs | Used in host-side PCIe expansion cards, not peripheral-side USB devices | Select only if designing a host-attached SATA expansion card, not a USB-connected storage device |
| Microchip USB5744 | USB 3.0 hub controller only; lacks SATA interface, ARM core, and AHCI logic - cannot perform protocol bridging | Designed for multi-port USB docking stations, not storage bridges | Choose only for USB port replication; does not replace TUSB9261IPVP's bridge function |
Compared with ASM1083 and USB5744, the TUSB9261IPVP uniquely integrates USB device controller, SATA host controller, and application processor in one die - enabling standalone, firmware-upgradable, bus-powered external storage solutions without external logic.
Availability
TUSB9261IPVP is available at Aetrix Electronics and suitable for external HDD enclosures, portable SSD docks, optical drive adapters, and industrial data loggers requiring stable component supply across extended temperature ranges and long product lifecycles.
Supply support for TUSB9261IPVP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company delivering analog and embedded processing solutions, with leadership in interface, power management, and microcontroller technologies since 1930.
The TUSB9261IPVP belongs to TI's USB bridge product line, designed specifically to simplify high-speed storage peripheral development by merging USB device, SATA host, and application firmware execution into a single programmable IC.
FAQ
What USB and SATA standards does the TUSB9261IPVP support?
The TUSB9261IPVP supports USB 3.0 SuperSpeed (5 Gbps), USB 2.0 High-Speed (480 Mbps), and Full-Speed (12 Mbps), with compliance verified under USB-IF TID 340730020. For SATA, it implements SATA Revision 2.6 with Gen1i/m and Gen2i/m support (1.5 Gbps and 3.0 Gbps), AHCI 1.3, and ATA/ATAPI-8 command sets. The TUSB9261IPVP achieves this through integrated PHYs and firmware-enforced protocol stacks - no external transceivers or controllers required.
Does the TUSB9261IPVP require external firmware storage?
Yes, the TUSB9261IPVP loads executable firmware from external SPI flash memory at power-up via its dedicated SPI interface (SPI_CS0, SCLK, DATA_IN, DATA_OUT). The on-chip 64 kB ROM contains only boot code; all application logic - including UASP/BOT protocol handlers, AHCI drivers, and GPIO/PWM control - resides in the external flash. This architecture enables field firmware updates over USB using TI-provided tools, and the TUSB9261IPVP supports dual-image flashing for safe rollback.
Can the TUSB9261IPVP operate with a single 3.3-V supply?
No, the TUSB9261IPVP requires two independent power rails: 1.1 V (VDD) for the core digital logic and 3.3 V (VDD33 and VDDA33) for I/O and analog circuitry. The 1.1-V rail supplies the ARM Cortex-M3 core and USB/SATA PHY digital sections, while the 3.3-V rails power GPIOs, USB 2.0 transceivers, and SATA analog front-end. TI recommends using the TPS650061 or TPS65024x multi-rail regulators to meet simultaneous startup sequencing and current demands (up to 340 mA on VDD).
How does the TUSB9261IPVP handle USB power negotiation and SATA device detection?
The TUSB9261IPVP initiates USB connection at SuperSpeed; if training fails, it automatically falls back to USB 2.0 High-Speed using DP pull-up. Simultaneously, its AHCI subsystem performs out-of-band (OOB) signaling to detect attached SATA devices and negotiate link speed (1.5/3.0 Gbps). Upon VBUS detection and successful enumeration, the TUSB9261IPVP presents BOT as primary interface and UASP as alternate - enabling host-driven interface selection. Device signature and IDENTIFY DEVICE commands are executed autonomously by firmware running on the TUSB9261IPVP.
What debug interfaces are available on the TUSB9261IPVP?
The TUSB9261IPVP provides IEEE 1149.1/1149.6 JTAG (TCK/TDI/TDO/TMS/TRSTz) for boundary scan, firmware download, and real-time core debugging, plus a UART (GPIO9/GPIO8) for ASCII-based debug logging and firmware diagnostics. Both interfaces are accessible without modifying the application firmware - JTAG operates at silicon level, while UART output is enabled by default in TI's reference firmware. These capabilities allow full visibility into TUSB9261IPVP operation during bring-up, validation, and field failure analysis.
TUSB9261IPVP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 64-TQFP Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Applications:
- HDD, CD, DVD Drive
- Interface:
- USB
- Voltage - Supply:
- -
- Supplier Device Package:
- 64-HTQFP (7x7)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
TUSB9261IPVP FAQ
1.How can I place an order for TUSB9261IPVP through Aetrix?
Please submit a Request for Quotation (RFQ) for TUSB9261IPVP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TUSB9261IPVP reliable?
The price and inventory of TUSB9261IPVP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TUSB9261IPVP is usually 5 days.
3.What payment methods are accepted for TUSB9261IPVP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TUSB9261IPVP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TUSB9261IPVP?
TUSB9261IPVP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TUSB9261IPVP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TUSB9261IPVP?
For technical support, including TUSB9261IPVP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TUSB9261IPVP requirements.
6.How does Aetrix verify that TUSB9261IPVP is sourced from the original manufacturer or authorized distributors?
All TUSB9261IPVP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TUSB9261IPVP meets industry standards.
7.What is the process for return or replacement of TUSB9261IPVP?
All TUSB9261IPVP units undergo pre-shipment inspection (PSI). If there is an issue with TUSB9261IPVP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TUSB9261IPVP part is unused and in its original packaging.
Return procedure for TUSB9261IPVP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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